diff options
| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-25 19:40:20 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-25 19:40:20 +0000 |
| commit | 1c2f49e74aa254c7c415641002c0c2f52ed42a5c (patch) | |
| tree | 39d3b9203e94f00a574afc9fb3941232c7c41178 /src/southbridge/amd | |
| parent | 5ee2bbb90cdc079e3e598c1f20237a32eed43e04 (diff) | |
to give ollie a look.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/cs5536/chip.h | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536.c | 32 |
2 files changed, 35 insertions, 2 deletions
diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h index 3e9be9938e..cb3cbe1039 100644 --- a/src/southbridge/amd/cs5536/chip.h +++ b/src/southbridge/amd/cs5536/chip.h @@ -4,7 +4,10 @@ extern struct chip_operations southbridge_amd_cs5536_ops; struct southbridge_amd_cs5536_config { - int none; + /* interrupt enable for LPC bus */ + int lpc_serirq_enable; /* how to enable, e.g. 0x80 */ + int lpc_irq; /* what to enable, e.g. 0x18 */ + int enable_gpio0_inta; /* almost always will be true */ }; #endif /* _SOUTHBRIDGE_AMD_CS5536 */ diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 953670f783..90ffe323ec 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -15,7 +15,37 @@ static void southbridge_init(struct device *dev) static void southbridge_enable(struct device *dev) { + struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; + msr_t msr; + struct device *gpiodev; + unsigned short gpiobase = MDD_GPIO; + printk_err("%s: dev is %p\n", __FUNCTION__, dev); + if (chip_info->lpc_serirq_enable) { + msr.lo = chip_info->lpc_serirq_enable; + msr.hi = 0; + wrmsr(MDD_LPC_SIRQ, msr); + } + if (chip_info->lpc_irq) { + msr.lo = chip_info->lpc_irq; + msr.hi = 0; + wrmsr(MDD_IRQM_LPC, msr); + } + + if (chip_info->enable_gpio0_inta){ + rdmsr(MDD_IRQM_ZHIGH, msr); + msr.lo |= 0x10; + wrmsr(MDD_IRQM_ZHIGH, msr); + /* todo: look the device up. But we know that gpiobase is 0x6100 */ + /* oh gosh, all the defines from AMD assume 6100. Don't bother looking up! */ + outl(GPIOL_0_SET|GPIOL_1_SET|GPIOL_3_SET, GPIOL_INPUT_ENABLE); + outl(GPIOL_0_SET,GPIOL_EVENTS_ENABLE); + /* magic stuff */ + outl(0x3081, GPIOL_INPUT_INVERT_ENABLE); + outl(GPIOL_0_SET, GPIO_MAPPER_X); + } + + } static void cs5536_pci_dev_enable_resources(device_t dev) @@ -34,7 +64,7 @@ static struct device_operations southbridge_ops = { .scan_bus = scan_static_bus, }; -static struct pci_driver cs5535_pci_driver __pci_driver = { +static struct pci_driver cs5536_pci_driver __pci_driver = { .ops = &southbridge_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_CS5536_ISA |