diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-03 20:41:04 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-10-04 14:30:52 +0200 |
| commit | 18cd8a64a46b85af5bf284165ce412188fc31948 (patch) | |
| tree | 8ce52f4941cfe435fd71b01abc93bc7655560812 /src/southbridge/amd | |
| parent | 5c22825c1924b1f5fb9cebff8e13b83792d3ecb9 (diff) | |
src/southbridge: Remove unnecessary semicolon
Change-Id: I52c3ec75d44290b758b6e952344aa9a768bc2617
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16857
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/cimx/sb700/smbus_spd.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs690/pcie.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/early_setup.c | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/early_setup.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sb800/early_setup.c | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/amd/cimx/sb700/smbus_spd.c b/src/southbridge/amd/cimx/sb700/smbus_spd.c index 281279b623..73261c4ab4 100644 --- a/src/southbridge/amd/cimx/sb700/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb700/smbus_spd.c @@ -120,7 +120,7 @@ static void setupFch(UINT16 ioBase) /* Enable SMBus MMIO. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); - LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); PciData8 |= BIT0; LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index 043c2eef5c..db65686a11 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -310,7 +310,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) /* step 6d: ASPM L1 for the southbridge link */ /* To enable L1s in the southbridge*/ - /* step 6e: ASPM L1 for GPP link(s) */; + /* step 6e: ASPM L1 for GPP link(s) */ set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13); set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12); set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4); diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index 2caa28bd79..2445310e6e 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -370,13 +370,13 @@ static void sb600_devices_por_init(void) printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); /* I don't know why CIM tried to write into a read-only reg! */ - /*pci_write_config8(dev, 0x0c, 0x20) */ ; + /*pci_write_config8(dev, 0x0c, 0x20); */ /* Arbiter enable. */ pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index ea7eb27161..e549e8a203 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -520,7 +520,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 10961596e0..82ad621c1e 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -468,7 +468,7 @@ static void sb800_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); |