diff options
author | Ronald G. Minnich <rminnich@gmail.com> | 2003-08-27 14:33:13 +0000 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2003-08-27 14:33:13 +0000 |
commit | fa2df758f226f5b06537c6e6f8e27072b94644c5 (patch) | |
tree | c5cb52825577c8d3825121283e020ad44a3fccd8 /src/southbridge/amd | |
parent | bee6575d7cdc065be6f8b83f9217602e44f29c20 (diff) |
support for new mobos and fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r-- | src/southbridge/amd/amd8151/Config.lb | 1 | ||||
-rw-r--r-- | src/southbridge/amd/amd8151/amd8151_agp3.c | 75 |
2 files changed, 76 insertions, 0 deletions
diff --git a/src/southbridge/amd/amd8151/Config.lb b/src/southbridge/amd/amd8151/Config.lb new file mode 100644 index 0000000000..00a91b6498 --- /dev/null +++ b/src/southbridge/amd/amd8151/Config.lb @@ -0,0 +1 @@ +driver amd8151_agp3.o diff --git a/src/southbridge/amd/amd8151/amd8151_agp3.c b/src/southbridge/amd/amd8151/amd8151_agp3.c new file mode 100644 index 0000000000..b7862feff9 --- /dev/null +++ b/src/southbridge/amd/amd8151/amd8151_agp3.c @@ -0,0 +1,75 @@ +/* + * Copyright 2003 Tyan + * + * Author: Yinghai Lu + */ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> + +static void agp3bridge_init(device_t dev) +{ + uint32_t dword; + + dword = pci_read_config8(dev, 0x04); + dword |= 0x07; + pci_write_config8(dev, 0x04, dword); + + return; +} + +static struct device_operations agp3bridge_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .init = agp3bridge_init, + .scan_bus = pci_scan_bridge, +}; + +static struct pci_driver agp3bridge_driver __pci_driver = { + .ops = &agp3bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7455, +}; + + +static void agp3dev_enable(device_t dev) +{ + uint32_t value; + + // AGP enable + value = pci_read_config32(dev, 0xa8); + value |= (1<<8); + pci_write_config32(dev, 0xa8, value); + + // linkA 8bit-->16bit + value = pci_read_config32(dev, 0xc4); + value |= (11<<24); + pci_write_config32(dev, 0xc4, value); + + // linkA 200-->600 + value = pci_read_config32(dev, 0xcc); + value |= (4<<8); + pci_write_config32(dev, 0xcc, value); + + + value = pci_read_config32(dev, 0x4); + value |= 6; + pci_write_config32(dev, 0x4, value); +} + +static struct device_operations agp3dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .init = 0, + .scan_bus = 0, + .enable = agp3dev_enable, +}; + +static struct pci_driver agp3dev_driver __pci_driver = { + .ops = &agp3dev_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7454, + +}; |