diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-06-30 07:34:36 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-07-14 19:43:03 +0200 |
| commit | 9f0a2be1658cf6d329aefac2660a53a465312468 (patch) | |
| tree | 7efd750712c5c829761e065605cee3b4b3f8b788 /src/southbridge/amd | |
| parent | 1110495de926db4b21b9969da522e5270c67f115 (diff) | |
AMD SPI: Optimise for longer writes
Leave it to the implementation of flash->write() to split the writes
to match SPI controller and SPI flash part restrictions. This allows
for some optimisation for auto-address-increment (AAI) commands.
Kconfig AMD_SB_SPI_TX_LEN can be kept as local.
Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6164
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/Kconfig | 9 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/spi.c | 15 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/spi.c | 14 |
3 files changed, 29 insertions, 9 deletions
diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 39aeb09455..867afcaf8b 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,12 +14,3 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig - -if CPU_AMD_AGESA - -config AMD_SB_SPI_TX_LEN - int - default 4 - depends on SPI_FLASH - -endif diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index f050a63f91..2aeb2c04c0 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -20,6 +20,7 @@ #include <stdlib.h> #include <string.h> #include <arch/io.h> +#include <console/console.h> #include <spi-generic.h> #include <device/device.h> #include <device/pci.h> @@ -101,6 +102,20 @@ int spi_xfer(struct spi_slave *slave, const void *dout, u8 count; bytesout--; + + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (bytesout > AMD_SB_SPI_TX_LEN) { + printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); + return -1; + } + readoffby1 = bytesout ? 0 : 1; #if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index e5b2407082..f38e691254 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -20,6 +20,7 @@ #include <stdlib.h> #include <string.h> #include <arch/io.h> +#include <console/console.h> #include <spi-generic.h> #include <device/device.h> #include <device/pci.h> @@ -74,6 +75,19 @@ int spi_xfer(struct spi_slave *slave, const void *dout, bytesout--; + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (bytesout > AMD_SB_SPI_TX_LEN) { + printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); + return -1; + } + readoffby1 = bytesout ? 0 : 1; readwrite = (bytesin + readoffby1) << 4 | bytesout; |