Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

24 files changed, 89 insertions, 89 deletions

diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c
index 1390065c09..2707ca6b43 100644
--- a/src/southbridge/amd/amd8111/amd8111.c
+++ b/src/southbridge/amd/amd8111/amd8111.c
@@ -13,8 +13,8 @@ void amd8111_enable(device_t dev)
 
 	/* See if we are on the bus behind the amd8111 pci bridge */
 	bus_dev = dev->bus->dev;
-	if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && 
-	    (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) 
+	if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) &&
+	    (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI))
 	{
 		unsigned devfn;
 		devfn = bus_dev->path.pci.devfn + (1 << 3);
@@ -33,7 +33,7 @@ void amd8111_enable(device_t dev)
 		return;
 	}
 	if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) ||
-	    (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) 
+	    (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA))
 	{
 		uint32_t id;
 		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
@@ -66,7 +66,7 @@ void amd8111_enable(device_t dev)
 
 struct chip_operations southbridge_amd_amd8111_ops = {
 	CHIP_NAME("AMD-8111 Southbridge")
-	/* This only called when this device is listed in the 
+	/* This only called when this device is listed in the
 	* static device tree.
 	*/
 	.enable_dev = amd8111_enable,
diff --git a/src/southbridge/amd/amd8111/amd8111_ac97.c b/src/southbridge/amd/amd8111/amd8111_ac97.c
index 697915e002..f49c9bfd5f 100644
--- a/src/southbridge/amd/amd8111/amd8111_ac97.c
+++ b/src/southbridge/amd/amd8111/amd8111_ac97.c
@@ -10,7 +10,7 @@
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x2c, 
+	pci_write_config32(dev, 0x2c,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c
index 32e3808a98..2ad54b78f6 100644
--- a/src/southbridge/amd/amd8111/amd8111_acpi.c
+++ b/src/southbridge/amd/amd8111/amd8111_acpi.c
@@ -28,7 +28,7 @@ static int lsmbus_recv_byte(device_t dev)
 
 	device = dev->path.i2c.device;
 	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-	
+
 	return do_smbus_recv_byte(res->base, device);
 }
 
@@ -51,7 +51,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
 
 	device = dev->path.i2c.device;
 	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-	
+
 	return do_smbus_read_byte(res->base, device, address);
 }
 
@@ -62,7 +62,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
 
 	device = dev->path.i2c.device;
 	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-	
+
 	return do_smbus_write_byte(res->base, device, address, val);
 }
 
@@ -109,7 +109,7 @@ static void acpi_init(struct device *dev)
 	 */
 	byte = pci_read_config8(dev, 0x41);
 	pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
-	
+
 	/* power on after power fail */
 	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
@@ -126,7 +126,7 @@ static void acpi_init(struct device *dev)
 	 */
 	byte = pci_read_config8(dev, 0x4a);
 	pci_write_config8(dev, 0x4a, byte | (1<<6));
-	
+
 	/* Throttle the CPU speed down for testing */
 	on = SLOW_CPU_OFF;
 	get_option(&on, "slow_cpu");
@@ -177,12 +177,12 @@ static void acpi_enable_resources(device_t dev)
 
 	/* Set the class code */
 	pci_write_config32(dev, 0x60, 0x06800000);
-	
+
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x7c, 
+	pci_write_config32(dev, 0x7c,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
@@ -204,7 +204,7 @@ static struct device_operations acpi_ops  = {
 	.init             = acpi_init,
 	.scan_bus         = scan_static_bus,
 	/*  We don't need amd8111_enable, chip ops takes care of it.
-	 *  It could be useful if these devices were not 
+	 *  It could be useful if these devices were not
 	 *  enabled by default.
 	 */
 //	.enable           = amd8111_enable,
diff --git a/src/southbridge/amd/amd8111/amd8111_ide.c b/src/southbridge/amd/amd8111/amd8111_ide.c
index 3b6f5a0a65..3299875187 100644
--- a/src/southbridge/amd/amd8111/amd8111_ide.c
+++ b/src/southbridge/amd/amd8111/amd8111_ide.c
@@ -42,7 +42,7 @@ static void ide_init(struct device *dev)
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x70, 
+	pci_write_config32(dev, 0x70,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 static struct pci_operations lops_pci = {
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index 85e217bb65..8fe4982721 100644
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -19,11 +19,11 @@
 static void enable_hpet(struct device *dev)
 {
 	unsigned long hpet_address;
-	
+
 	pci_write_config32(dev,0xa0, 0xfed00001);
 	hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
 	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
-	
+
 }
 
 static void lpc_init(struct device *dev)
@@ -40,7 +40,7 @@ static void lpc_init(struct device *dev)
 
 	/* posted memory write enable */
 	byte = pci_read_config8(dev, 0x46);
-	pci_write_config8(dev, 0x46, byte | (1<<0)); 
+	pci_write_config8(dev, 0x46, byte | (1<<0));
 
 	/* Enable 5Mib Rom window */
 	byte = pci_read_config8(dev, 0x43);
@@ -65,11 +65,11 @@ static void lpc_init(struct device *dev)
 	pci_write_config8(dev, 0x40, byte);
 	nmi_option = NMI_OFF;
 	get_option(&nmi_option, "nmi");
-	if (nmi_option) {			
+	if (nmi_option) {
 		byte |= (1 << 7); /* set NMI */
 		pci_write_config8(dev, 0x40, byte);
 	}
-	
+
 	/* Initialize the real time clock */
 	rtc_init(0);
 
@@ -114,7 +114,7 @@ static void amd8111_lpc_enable_resources(device_t dev)
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x70, 
+	pci_write_config32(dev, 0x70,
 			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c
index 8818b51b40..4ab7212eda 100644
--- a/src/southbridge/amd/amd8111/amd8111_nic.c
+++ b/src/southbridge/amd/amd8111/amd8111_nic.c
@@ -25,20 +25,20 @@ typedef enum {
 	ASF_INIT_DONE_ALIAS	= (1 << 29),
 	/* VAL2 */
 	JUMBO			= (1 << 21),
-	VSIZE			= (1 << 20),	
+	VSIZE			= (1 << 20),
 	VLONLY			= (1 << 19),
-	VL_TAG_DEL		= (1 << 18),	
+	VL_TAG_DEL		= (1 << 18),
 	/* VAL1 */
-	EN_PMGR			= (1 << 14),			
+	EN_PMGR			= (1 << 14),
 	INTLEVEL		= (1 << 13),
-	FORCE_FULL_DUPLEX	= (1 << 12),	
-	FORCE_LINK_STATUS	= (1 << 11),	
-	APEP			= (1 << 10),	
-	MPPLBA			= (1 << 9),	
+	FORCE_FULL_DUPLEX	= (1 << 12),
+	FORCE_LINK_STATUS	= (1 << 11),
+	APEP			= (1 << 10),
+	MPPLBA			= (1 << 9),
 	/* VAL0 */
-	RESET_PHY_PULSE		= (1 << 2),	
-	RESET_PHY		= (1 << 1),	
-	PHY_RST_POL		= (1 << 0),	
+	RESET_PHY_PULSE		= (1 << 2),
+	RESET_PHY		= (1 << 1),
+	PHY_RST_POL		= (1 << 0),
 }CMD3_BITS;
 
 static void nic_init(struct device *dev)
@@ -72,7 +72,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 static struct pci_operations lops_pci = {
 	.set_subsystem = lpci_set_subsystem,
 };
-	
+
 static struct device_operations nic_ops  = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/amd8111_reset.c
index 9b26bcb90d..c96e898aea 100644
--- a/src/southbridge/amd/amd8111/amd8111_reset.c
+++ b/src/southbridge/amd/amd8111/amd8111_reset.c
@@ -67,7 +67,7 @@ void hard_reset(void)
 	 */
 	bus = node_link_to_bus(node, link);
 	dev = pci_locate_device_on_bus(
-		PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), 
+		PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA),
 		bus);
 
 	/* Reset */
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.c b/src/southbridge/amd/amd8111/amd8111_smbus.c
index 2554fd0c5e..0a0c58dce3 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.c
+++ b/src/southbridge/amd/amd8111/amd8111_smbus.c
@@ -13,7 +13,7 @@
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x44, 
+	pci_write_config32(dev, 0x44,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h
index b5799666e9..fe9b3bff8c 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.h
+++ b/src/southbridge/amd/amd8111/amd8111_smbus.h
@@ -27,7 +27,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
 			break;
 		}
 		if(loops == (SMBUS_TIMEOUT / 2)) {
-			outw(inw(smbus_io_base + SMBGSTATUS), 
+			outw(inw(smbus_io_base + SMBGSTATUS),
 				smbus_io_base + SMBGSTATUS);
 		}
 	} while(--loops);
@@ -41,7 +41,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 	do {
 		unsigned short val;
 		smbus_delay();
-		
+
 		val = inw(smbus_io_base + SMBGSTATUS);
 		if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) {
 			break;
@@ -58,7 +58,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
 		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 	}
-	
+
 	/* setup transaction */
 	/* disable interrupts */
 	outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
@@ -103,7 +103,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
 		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 	}
-	
+
 	/* setup transaction */
 	/* disable interrupts */
 	outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
@@ -146,7 +146,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
 		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 	}
-	
+
 	/* setup transaction */
 	/* disable interrupts */
 	outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
diff --git a/src/southbridge/amd/amd8111/amd8111_usb.c b/src/southbridge/amd/amd8111/amd8111_usb.c
index f1c331dbaf..13dccf435b 100644
--- a/src/southbridge/amd/amd8111/amd8111_usb.c
+++ b/src/southbridge/amd/amd8111/amd8111_usb.c
@@ -12,7 +12,7 @@
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x70, 
+	pci_write_config32(dev, 0x70,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
diff --git a/src/southbridge/amd/amd8111/amd8111_usb2.c b/src/southbridge/amd/amd8111/amd8111_usb2.c
index 3aa5211dd0..89115c3bbe 100644
--- a/src/southbridge/amd/amd8111/amd8111_usb2.c
+++ b/src/southbridge/amd/amd8111/amd8111_usb2.c
@@ -11,7 +11,7 @@
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x70, 
+	pci_write_config32(dev, 0x70,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
@@ -23,7 +23,7 @@ static struct pci_operations lops_pci = {
 
 static void amd8111_usb2_enable(device_t dev)
 {
-	// Due to buggy USB2 we force it to disable. 
+	// Due to buggy USB2 we force it to disable.
 	dev->enabled = 0;
 	amd8111_enable(dev);
 	printk(BIOS_DEBUG, "USB2 disabled.\n");
diff --git a/src/southbridge/amd/amd8111/chip.h b/src/southbridge/amd/amd8111/chip.h
index 6c97ef2232..601038c441 100644
--- a/src/southbridge/amd/amd8111/chip.h
+++ b/src/southbridge/amd/amd8111/chip.h
@@ -1,7 +1,7 @@
 #ifndef AMD8111_CHIP_H
 #define AMD8111_CHIP_H
 
-struct southbridge_amd_amd8111_config 
+struct southbridge_amd_amd8111_config
 {
 	unsigned int ide0_enable : 1;
 	unsigned int ide1_enable : 1;
diff --git a/src/southbridge/amd/amd8131-disable/amd8131_bridge.c b/src/southbridge/amd/amd8131-disable/amd8131_bridge.c
index bcb89fa22a..e90f497d95 100644
--- a/src/southbridge/amd/amd8131-disable/amd8131_bridge.c
+++ b/src/southbridge/amd/amd8131-disable/amd8131_bridge.c
@@ -112,5 +112,5 @@ static const struct pci_driver ioapic_driver __pci_driver = {
 	.ops    = &ioapic_ops,
 	.vendor = PCI_VENDOR_ID_AMD,
 	.device = 0x7451,
-	
+
 };
diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c
index 04930517e6..ae2c4cffcb 100644
--- a/src/southbridge/amd/amd8131/amd8131_bridge.c
+++ b/src/southbridge/amd/amd8131/amd8131_bridge.c
@@ -121,7 +121,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
 		}
 	}
 	/* Errata #56 additional limits when the bus runs at 133Mhz */
-	if (info->errata_56 && 
+	if (info->errata_56 &&
 		(PCI_X_SSTATUS_MFREQ(info->sstatus) == PCI_X_SSTATUS_MODE1_133MHZ))
 	{
 		unsigned limit_read;
@@ -131,7 +131,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
 		if (sib_funcs == 0) {
 			/* 2k reads */
 			limit_read = 2;
-		} 
+		}
 		else if (sib_funcs <= 1) {
 			/* 1k reads */
 			limit_read = 1;
@@ -226,8 +226,8 @@ static unsigned int amd8131_scan_bus(struct bus *bus,
 	 * we are running at 133Mhz and have a 4 function device.
 	 * see errata #56
 	 */
-	if (!bus->children || 
-		(info.errata_56 && 
+	if (!bus->children ||
+		(info.errata_56 &&
 			(info.max_func >= 3) &&
 			(PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_MODE1_133MHZ)))
 	{
@@ -242,7 +242,7 @@ static unsigned int amd8131_scan_bus(struct bus *bus,
 		pcix_misc = pci_read_config32(bus->dev, 0x40);
 		pcix_misc &= ~(0x1f << 16);
 		pci_write_config32(bus->dev, 0x40, pcix_misc);
-		
+
 		return max;
 	}
 
@@ -284,7 +284,7 @@ static void amd8131_pcix_init(device_t dev)
 	byte = pci_read_config8(dev, 0x04);
         byte |= 0x10;
         pci_write_config8(dev, 0x04, byte);
- 	
+
 	/* Set drive strength */
 	word = pci_read_config16(dev, 0xe0);
         word = 0x0404;
@@ -292,7 +292,7 @@ static void amd8131_pcix_init(device_t dev)
 	word = pci_read_config16(dev, 0xe4);
         word = 0x0404;
         pci_write_config16(dev, 0xe4, word);
-	
+
 	/* Set impedance */
 	word = pci_read_config16(dev, 0xe8);
         word = 0x0404;
@@ -303,7 +303,7 @@ static void amd8131_pcix_init(device_t dev)
 	word = pci_read_config16(dev, 0x4c);
         word |= 1;
         pci_write_config16(dev, 0x4c, word);
-	
+
 	/* Set split transaction limits */
 	word = pci_read_config16(dev, 0xa8);
         pci_write_config16(dev, 0xaa, word);
@@ -315,12 +315,12 @@ static void amd8131_pcix_init(device_t dev)
 	dword = pci_read_config32(dev, 0x04);
         dword |= (1<<8);
         pci_write_config32(dev, 0x04, dword);
- 	
+
 	/* system and error parity enable */
 	dword = pci_read_config32(dev, 0x3c);
         dword |= (3<<16);
         pci_write_config32(dev, 0x3c, dword);
- 	
+
 	/* NMI enable */
 	nmi_option = NMI_OFF;
 	get_option(&nmi_option, "nmi");
@@ -329,7 +329,7 @@ static void amd8131_pcix_init(device_t dev)
         	dword |= (1<<0);
         	pci_write_config32(dev, 0x44, dword);
 	}
- 	
+
 	/* Set up CRC flood enable */
 	dword = pci_read_config32(dev, 0xc0);
 	if(dword) {  /* do device A only */
@@ -349,7 +349,7 @@ static void bridge_read_resources(struct device *dev)
 {
 	struct resource *res;
 	pci_bus_read_resources(dev);
-	res = find_resource(dev, PCI_MEMORY_BASE);	
+	res = find_resource(dev, PCI_MEMORY_BASE);
 	if (res) {
 		res->limit = 0xffffffffffULL;
 	}
@@ -428,5 +428,5 @@ static const struct pci_driver ioapic_driver __pci_driver = {
 	.ops    = &ioapic_ops,
 	.vendor = PCI_VENDOR_ID_AMD,
 	.device = 0x7451,
-	
+
 };
diff --git a/src/southbridge/amd/amd8132/amd8132_bridge.c b/src/southbridge/amd/amd8132/amd8132_bridge.c
index 2c18c5ebcb..e8283baa50 100644
--- a/src/southbridge/amd/amd8132/amd8132_bridge.c
+++ b/src/southbridge/amd/amd8132/amd8132_bridge.c
@@ -114,7 +114,7 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr)
 	max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
 	max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
 
-	if (info->rev == 0x01) { // only a1 need it 
+	if (info->rev == 0x01) { // only a1 need it
 		/* Errata #53 Limit the number of split transactions to avoid starvation */
 		if (sibs >= 2) {
 			/* At most 2 outstanding split transactions when we have
@@ -186,7 +186,7 @@ static unsigned int amd8132_scan_bus(struct bus *bus,
 	amd8132_walk_children(bus, amd8132_count_dev, &info);
 
 #if 0
-	/* Disable the bus if there are no devices on it 
+	/* Disable the bus if there are no devices on it
 	 */
 	if (!bus->children)
 	{
@@ -201,7 +201,7 @@ static unsigned int amd8132_scan_bus(struct bus *bus,
 		pcix_misc = pci_read_config32(bus->dev, 0x40);
 		pcix_misc &= ~(0x1f << 16);
 		pci_write_config32(bus->dev, 0x40, pcix_misc);
-		
+
 		return max;
 	}
 #endif
@@ -229,7 +229,7 @@ static void amd8132_pcix_init(device_t dev)
 	uint32_t dword;
 	uint8_t byte;
 	unsigned chip_rev;
-        
+
 	/* Find the revision of the 8132 */
         chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
 
@@ -259,7 +259,7 @@ static void amd8132_pcix_init(device_t dev)
 	dword = pci_read_config32(dev, 0x04);
         dword |= (1<<8);
         pci_write_config32(dev, 0x04, dword);
- 	
+
 	/* system and error parity enable */
 	dword = pci_read_config32(dev, 0x3c);
         dword |= (3<<16);
@@ -267,7 +267,7 @@ static void amd8132_pcix_init(device_t dev)
 
         dword = pci_read_config32(dev, 0x40);
 //        dword &= ~(1<<31); /* WriteChainEnable */
-	dword |= (1<<31); 
+	dword |= (1<<31);
 	dword |= (1<<7);// must set to 1
 	dword |= (3<<21); //PCIErrorSerrDisable
         pci_write_config32(dev, 0x40, dword);
@@ -335,7 +335,7 @@ static void bridge_read_resources(struct device *dev)
 {
 	struct resource *res;
 	pci_bus_read_resources(dev);
-	res = find_resource(dev, PCI_MEMORY_BASE);	
+	res = find_resource(dev, PCI_MEMORY_BASE);
 	if (res) {
 		res->limit = 0xffffffffffULL;
 	}
@@ -450,5 +450,5 @@ static const struct pci_driver ioapic_driver __pci_driver = {
 	.ops    = &ioapic_ops,
 	.vendor = PCI_VENDOR_ID_AMD,
 	.device = 0x7459,
-	
+
 };
diff --git a/src/southbridge/amd/amd8151/amd8151_agp3.c b/src/southbridge/amd/amd8151/amd8151_agp3.c
index 93c7992810..5d673f6ae8 100644
--- a/src/southbridge/amd/amd8151/amd8151_agp3.c
+++ b/src/southbridge/amd/amd8151/amd8151_agp3.c
@@ -38,7 +38,7 @@ static const struct pci_driver agp3bridge_driver __pci_driver = {
 static void agp3dev_enable(device_t dev)
 {
 	uint32_t value;
-	
+
 	/* AGP enable */
 	value = pci_read_config32(dev, 0xa8);
 	value |= (3<<8)|2; //AGP 8x
@@ -71,5 +71,5 @@ static struct device_operations agp3dev_ops = {
 static const struct pci_driver agp3dev_driver __pci_driver = {
 	.ops    = &agp3dev_ops,
 	.vendor = PCI_VENDOR_ID_AMD,
-	.device = 0x7454, //AGP Device	
+	.device = 0x7454, //AGP Device
 };
diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c
index 6f203558e3..50b62df0c3 100644
--- a/src/southbridge/amd/cs5535/cs5535.c
+++ b/src/southbridge/amd/cs5535/cs5535.c
@@ -21,7 +21,7 @@ static void nvram_on(struct device *dev)
 	/* Set positive decode on ROM */
 	/* Also, there is no apparent reason to turn off the devoce on the */
 	/* IDE devices */
-	
+
 	reg = pci_read_config8(dev, 0x5b);
 	reg |= 1 << 5;	/* ROM Decode */
 	reg |= 1 << 3;	/* Primary IDE decode */
@@ -43,7 +43,7 @@ static void nvram_on(struct device *dev)
 #endif
 }
 
-	
+
 static void southbridge_init(struct device *dev)
 {
 	printk(BIOS_SPEW, "cs5535: %s\n", __func__);
diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c
index fbb3647578..91dc852012 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_setup.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c
@@ -8,13 +8,13 @@
  *
  */
 
-#define CS5535_GLINK_PORT_NUM	0x02	/* the geode link port number to the CS5535 */       
+#define CS5535_GLINK_PORT_NUM	0x02	/* the geode link port number to the CS5535 */
 #define CS5535_DEV_NUM 		0x0F	/* default PCI device number for CS5535 */
 
 /**
  * @brief Setup PCI IDSEL for CS5535
  *
- * 
+ *
  */
 
 static void cs5535_setup_extmsr(void)
diff --git a/src/southbridge/amd/cs5535/cs5535_early_smbus.c b/src/southbridge/amd/cs5535/cs5535_early_smbus.c
index 6ff46338f6..ec801f02a8 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_smbus.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_smbus.c
@@ -18,7 +18,7 @@ static int cs5535_enable_smbus(void)
 	/* Setup SMBus host controller address to 0xEF */
 	val = inb(SMBUS_IO_BASE + SMB_ADD);
 	val |= (0xEF | SMB_ADD_SAEN);
-	outb(val, SMBUS_IO_BASE + SMB_ADD); 
+	outb(val, SMBUS_IO_BASE + SMB_ADD);
 }
 
 static int smbus_read_byte(unsigned device, unsigned address)
diff --git a/src/southbridge/amd/cs5535/cs5535_smbus.h b/src/southbridge/amd/cs5535/cs5535_smbus.h
index 9cf55ba29c..799e226f5e 100644
--- a/src/southbridge/amd/cs5535/cs5535_smbus.h
+++ b/src/southbridge/amd/cs5535/cs5535_smbus.h
@@ -105,7 +105,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device
 	unsigned char val;
 	unsigned long loops;
 	loops = SMBUS_TIMEOUT;
-                        
+
 	/* send the slave address */
 	outb(device, smbus_io_base + SMB_SDA);
 
@@ -123,7 +123,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device
 			break;
 		}
 	} while(--loops);
-	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;	
+	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 }
 
 static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
@@ -149,7 +149,7 @@ static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
 			break;
 		}
 	} while(--loops);
-	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;	
+	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 }
 
 static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
diff --git a/src/southbridge/amd/cs5536/Kconfig b/src/southbridge/amd/cs5536/Kconfig
index b6884b7fa9..e7caf5e27a 100644
--- a/src/southbridge/amd/cs5536/Kconfig
+++ b/src/southbridge/amd/cs5536/Kconfig
@@ -26,5 +26,5 @@ config UDELAY_TSC
 	default y
 	depends on SOUTHBRIDGE_AMD_CS5536
 
-	
+
 
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 43f3b1290e..11679278f8 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -247,7 +247,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb)
 
 	isa_dma_init();
 }
-			
+
 
 /**
  * Depending on settings in the config struct, enable COM1 or COM2 or both.
@@ -263,8 +263,8 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
 	u16 addr = 0;
 	u32 gpio_addr;
 	device_t dev;
-	
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
 			PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
 	gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
 	gpio_addr &= ~1;	/* Clear I/O bit */
@@ -431,7 +431,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 	msr_t msr;
 	device_t dev;
 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
 			PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
 	if (dev) {
 
@@ -452,7 +452,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 		write32(bar + HCCPARAMS, 0x00005012);
 	}
 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
 			PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 	if (dev) {
 		bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -480,7 +480,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 	 * - set PADEN (former OTGPADEN) bit in uoc register
 	 * - set APU bit in uoc register */
 	if (sb->enable_USBP4_device) {
-		dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+		dev = dev_find_device(PCI_VENDOR_ID_AMD,
 				PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
 		if (dev) {
 			bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -499,13 +499,13 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 	}
 
 	/* Disable virtual PCI UDC and OTG headers */
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
 			PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
 	if (dev) {
 		pci_write_config32(dev, 0x7C, 0xDEADBEEF);
 	}
 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
 			PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 	if (dev) {
 		pci_write_config32(dev, 0x7C, 0xDEADBEEF);
@@ -513,14 +513,14 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 }
 
 /****************************************************************************
- * 
- * 	ChipsetInit 
+ *
+ * 	ChipsetInit
  *
  *	Called from northbridge init (Pre-VSA).
  *
  *	NOTE! This function is NOT called if the CS5536 is combined with
  *	an AMD Geode GX2. It's ONLY used on Geode LX based systems.
- * 
+ *
  ****************************************************************************/
 void chipsetinit(void)
 {
@@ -530,7 +530,7 @@ void chipsetinit(void)
 	struct southbridge_amd_cs5536_config *sb;
 	struct msrinit *csi;
 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
 			PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
 
 	if (!dev) {
diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h
index 073bb3ea59..797ac92764 100644
--- a/src/southbridge/amd/cs5536/cs5536.h
+++ b/src/southbridge/amd/cs5536/cs5536.h
@@ -465,7 +465,7 @@
 #define FLASH_IO_256B		0x0000FF00
 
 #if !defined(ASSEMBLY) && !defined(__ROMCC__)
-#if defined(__PRE_RAM__) 
+#if defined(__PRE_RAM__)
 void cs5536_setup_onchipuart(int uart);
 void cs5536_disable_internal_uart(void);
 #else
diff --git a/src/southbridge/amd/cs5536/cs5536_smbus2.h b/src/southbridge/amd/cs5536/cs5536_smbus2.h
index 3613b3d37b..dea08a437c 100644
--- a/src/southbridge/amd/cs5536/cs5536_smbus2.h
+++ b/src/southbridge/amd/cs5536/cs5536_smbus2.h
@@ -309,7 +309,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base,
 			(unsigned char *)&data, 1);
 }
 
-static inline int do_smbus_write_word(unsigned smbus_io_base, 
+static inline int do_smbus_write_word(unsigned smbus_io_base,
 		unsigned char device, unsigned char address, unsigned short data)
 {
 	return _dowrite(smbus_io_base, device, address, (unsigned char *)&data,