sb/amd: Remove dropped platforms

This code is now unused by any platform. Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69120 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
author: Arthur Heymans <arthur@aheymans.xyz> 2022-11-01 23:38:19 +0100
committer: Arthur Heymans <arthur@aheymans.xyz> 2022-11-07 13:59:17 +0000
commit: 03a6ccd20d9bb54e3a009269b8e454ee8a2e3051 (patch)
tree: 8f8b9c6fc6e383e5e7aa4f9631119a8517859d04 /src/southbridge/amd
parent: 1a010236cf922fc28cfb36b604bdf17a9ea3cb82 (diff)
84 files changed, 1 insertions, 8324 deletions
diff --git a/src/southbridge/amd/agesa/Kconfig b/src/southbridge/amd/agesa/Kconfig
deleted file mode 100644
index 1627a7a8b0..0000000000
--- a/src/southbridge/amd/agesa/Kconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-source "src/southbridge/amd/agesa/hudson/Kconfig"
diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc
deleted file mode 100644
index 21985561bd..0000000000
--- a/src/southbridge/amd/agesa/Makefile.inc
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
deleted file mode 100644
index 5ea6b1a2e0..0000000000
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ /dev/null
@@ -1,180 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config SOUTHBRIDGE_AMD_AGESA_HUDSON
-	bool
-
-config SOUTHBRIDGE_AMD_AGESA_YANGTZE
-	bool
-
-if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
-
-config SOUTHBRIDGE_SPECIFIC_OPTIONS
-	def_bool y
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_CF9_RESET
-	select HAVE_CF9_RESET_PREPARE
-	select SOC_AMD_COMMON
-	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
-	select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
-	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
-	select BOOT_DEVICE_SUPPORTS_WRITES
-
-config EHCI_BAR
-	hex
-	default 0xfef00000
-
-config HUDSON_XHCI_ENABLE
-	bool "Enable Hudson XHCI Controller"
-	default y if HUDSON_XHCI_FWM
-	help
-	  The XHCI controller must be enabled and the XHCI firmware
-	  must be added in order to have USB 3.0 support configured
-	  by coreboot. The OS will be responsible for enabling the XHCI
-	  controller if the XHCI firmware is available but the
-	  XHCI controller is not enabled by coreboot.
-
-config HUDSON_XHCI_FWM
-	bool "Add xhci firmware"
-	default y if USE_BLOBS
-	help
-	  Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
-
-config HUDSON_IMC_ENABLE
-	bool
-	default n
-
-config HUDSON_IMC_FWM
-	bool "Add IMC firmware"
-	depends on HUDSON_IMC_ENABLE
-	default y if USE_BLOBS
-	select SPI_FLASH_HAS_VOLATILE_GROUP if SPI_FLASH
-	help
-	  Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
-
-config HUDSON_GEC_FWM
-	bool
-	default n
-	help
-	  Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
-	  Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
-
-config HUDSON_XHCI_FWM_FILE
-	string "XHCI firmware path and filename"
-	default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
-	default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
-	depends on HUDSON_XHCI_FWM
-
-config HUDSON_IMC_FWM_FILE
-	string "IMC firmware path and filename"
-	default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
-	default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
-	depends on HUDSON_IMC_FWM
-
-config HUDSON_GEC_FWM_FILE
-	string "GEC firmware path and filename"
-	default "3rdparty/blobs/southbridge/amd/hudson/gec.bin"  if SOUTHBRIDGE_AMD_AGESA_HUDSON
-	default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin"  if SOUTHBRIDGE_AMD_AGESA_YANGTZE
-	depends on HUDSON_GEC_FWM
-
-config HUDSON_SATA_MODE
-	int "SATA Mode"
-	default 2
-	range 0 6
-	help
-	  Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
-	  The default is NATIVE.
-	  0: NATIVE mode does not require a ROM.
-	  1: RAID mode must have the two ROM files.
-	  2: AHCI may work with or without AHCI ROM. It depends on the payload support.
-	     For example, seabios does not require the AHCI ROM.
-	  3: LEGACY IDE
-	  4: IDE to AHCI
-	  5: AHCI7804: ROM Required, and AMD driver required in the OS.
-	  6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
-
-comment "NATIVE"
-	depends on HUDSON_SATA_MODE = 0
-
-comment "RAID"
-	depends on HUDSON_SATA_MODE = 1
-
-comment "AHCI"
-	depends on HUDSON_SATA_MODE = 2
-
-comment "LEGACY IDE"
-	depends on HUDSON_SATA_MODE = 3
-
-comment "IDE to AHCI"
-	depends on HUDSON_SATA_MODE = 4
-
-comment "AHCI7804"
-	depends on HUDSON_SATA_MODE = 5
-
-comment "IDE to AHCI7804"
-	depends on HUDSON_SATA_MODE = 6
-
-if HUDSON_SATA_MODE = 2 || HUDSON_SATA_MODE = 5
-
-config AHCI_ROM_ID
-	string  "AHCI device PCI IDs"
-	default "1022,7801" if HUDSON_SATA_MODE = 2
-	default "1022,7804" if HUDSON_SATA_MODE = 5
-
-config HUDSON_AHCI_ROM
-	bool "Add a AHCI ROM"
-
-config AHCI_ROM_FILE
-	string "AHCI ROM path and filename"
-	depends on HUDSON_AHCI_ROM
-	default "src/southbridge/amd/agesa/hudson/ahci.bin"
-
-endif
-
-if HUDSON_SATA_MODE = 1
-
-config RAID_ROM_ID
-	string "RAID device PCI IDs"
-	default "1022,7802"
-	help
-	  1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
-
-config RAID_ROM_FILE
-	string "RAID ROM path and filename"
-	default "src/southbridge/amd/agesa/hudson/raid.bin"
-
-config RAID_MISC_ROM_FILE
-	string "RAID Misc ROM path and filename"
-	default "src/southbridge/amd/agesa/hudson/misc.bin"
-
-config RAID_MISC_ROM_POSITION
-	hex "RAID Misc ROM Position"
-	default 0xFFF00000
-	help
-	  The RAID ROM requires that the MISC ROM is located between the range
-	  0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
-	  The CONFIG_ROM_SIZE must be larger than 0x100000.
-
-endif
-
-config HUDSON_LEGACY_FREE
-	bool "System is legacy free"
-	help
-	  Select y if there is no keyboard controller in the system.
-	  This sets variables in AGESA and ACPI.
-
-config ACPI_ENABLE_THERMAL_ZONE
-	bool
-	default y
-
-endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
-
-if SOUTHBRIDGE_AMD_AGESA_YANGTZE
-	config AZ_PIN
-		hex
-		default 0xaa
-		help
-		  bit 1,0 - pin 0
-		  bit 3,2 - pin 1
-		  bit 5,4 - pin 2
-		  bit 7,6 - pin 3
-endif
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
deleted file mode 100644
index b8eb5b9b37..0000000000
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ /dev/null
@@ -1,79 +0,0 @@
-
-CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/agesa/hudson
-CPPFLAGS_x86_64 += -I$(src)/southbridge/amd/agesa/hudson
-
-romstage-y += smbus.c smbus_spd.c
-ramstage-y += hudson.c
-ramstage-y += usb.c
-ramstage-y += lpc.c
-ramstage-y += sm.c
-ramstage-y += ide.c
-ramstage-y += sata.c
-ramstage-y += hda.c
-ramstage-y += pci.c
-ramstage-y += pcie.c
-ramstage-y += sd.c
-
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
-
-bootblock-y += bootblock.c
-bootblock-y += early_setup.c
-bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
-
-romstage-y += enable_usbdebug.c
-ramstage-y += enable_usbdebug.c
-romstage-y += early_setup.c
-
-ramstage-$(CONFIG_SPI_FLASH) += spi.c
-ramstage-y += resume.c ramtop.c
-
-romstage-y += ramtop.c
-postcar-y += ramtop.c
-
-romstage-y += imc.c
-ramstage-y += imc.c
-
-all-y += reset.c
-
-smm-y += smihandler.c smi_util.c
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c
-
-# ROMSIG At ROMBASE + 0x20000:
-# +-----------+---------------+----------------+------------+
-# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM    |
-# +-----------+---------------+----------------+------------+
-# EC ROM should be 64K aligned.
-
-HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1)
-
-ifdef CONFIG_HUDSON_AHCI_ROM
-stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID))
-cbfs-files-y += pci$(stripped_ahci_rom_id).rom
-pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE))
-pci$(stripped_ahci_rom_id).rom-type := optionrom
-pci$(stripped_ahci_rom_id).rom-required := Hudson AHCI Option ROM (Contact your AMD representative)
-endif
-
-add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
-
-OPT_HUDSON_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_XHCI_FWM_FILE), --xhci)
-OPT_HUDSON_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_IMC_FWM_FILE), --imc)
-OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILE), --gec)
-
-$(obj)/amdfw.rom:	$(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \
-			$(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \
-			$(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \
-			$(AMDFWTOOL)
-	rm -f $@
-	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
-	$(AMDFWTOOL) \
-		$(OPT_HUDSON_XHCI_FWM_FILE) \
-		$(OPT_HUDSON_IMC_FWM_FILE) \
-		$(OPT_HUDSON_GEC_FWM_FILE) \
-		--flashsize $(CONFIG_ROM_SIZE) \
-		--output	$@
-
-cbfs-files-y += apu/amdfw
-apu/amdfw-file := $(obj)/amdfw.rom
-apu/amdfw-position := $(HUDSON_FWM_POSITION)
-apu/amdfw-type := raw
diff --git a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl b/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl
deleted file mode 100644
index 6fe5e33cb8..0000000000
--- a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
-Field(IMIO , ByteAcc, NoLock, Preserve) {
-	IMCX,8,
-	IMCA,8
-}
-
-IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
-	Offset(0x80),
-	MSTI, 8,
-	MITS, 8,
-	MRG0, 8,
-	MRG1, 8,
-	MRG2, 8,
-	MRG3, 8,
-}
-
-Method(WACK, 0)
-{
-	Local0 = 0
-	Local1 = 50
-	While ((Local0 != 0xfa) && (Local1 > 0)) {
-		Local0 = MRG0
-		Sleep(10)
-		Local1--
-	}
-}
-
-//Init
-Method (ITZE, 0)
-{
-	MRG0 = 0
-	MRG1 = 0xb5
-	MRG2 = 0
-	MSTI = 0x96
-	WACK()
-
-	MRG0 = 0
-	MRG1 = 0
-	MRG2 = 0
-	MSTI = 0x80
-	WACK()
-
-	Local0 = MRG2 | 0x01
-
-	MRG0 = 0
-	MRG1 = 0
-	MRG2 = Local0
-	MSTI = 0x81
-	WACK()
-}
diff --git a/src/southbridge/amd/agesa/hudson/acpi/audio.asl b/src/southbridge/amd/agesa/hudson/acpi/audio.asl
deleted file mode 100644
index 58f566e70b..0000000000
--- a/src/southbridge/amd/agesa/hudson/acpi/audio.asl
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device(AZHD) {	/* 0:14.2 - HD Audio */
-	Name(_ADR, 0x00140002)
-	OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
-		Field(AZPD, AnyAcc, NoLock, Preserve) {
-		offset (0x42),
-		NSDI, 1,
-		NSDO, 1,
-		NSEN, 1,
-		offset (0x44),
-		IPCR, 4,
-		offset (0x54),
-		PWST, 2,
-		, 6,
-		PMEB, 1,
-		, 6,
-		PMST, 1,
-		offset (0x62),
-		MMCR, 1,
-		offset (0x64),
-		MMLA, 32,
-		offset (0x68),
-		MMHA, 32,
-		offset (0x6C),
-		MMDT, 16,
-	}
-
-	Method (_INI, 0, NotSerialized)
-	{
-		NSEN = 0
-		NSDO = 1
-		NSDI = 1
-	}
-} /* end AZHD */
diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl
deleted file mode 100644
index b87b9e4946..0000000000
--- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl
+++ /dev/null
@@ -1,166 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* System Bus */
-/*  _SB.PCI0 */
-
-/* Operating System Capabilities Method */
-Method(_OSC,4)
-{
-	/* Check for proper PCI/PCIe UUID */
-	If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
-	{
-		/* Let OS control everything */
-		Return (Arg3)
-	} Else {
-		CreateDWordField(Arg3,0,CDW1)
-		CDW1 |= 4	// Unrecognized UUID
-		Return (Arg3)
-	}
-}
-
-/* Describe the Southbridge devices */
-
-/* 0:11.0 - SATA */
-Device(STCR) {
-	Name(_ADR, 0x00110000)
-	#include "acpi/sata.asl"
-} /* end STCR */
-
-/* 0:14.0 - SMBUS */
-Device(SBUS) {
-	Name(_ADR, 0x00140000)
-} /* end SBUS */
-
-#include "usb.asl"
-
-/* 0:14.2 - HD Audio */
-#include "audio.asl"
-
-/* 0:14.3 - LPC */
-#include "lpc.asl"
-
-/* 0:14.7 - SD Controller */
-Device(SDCN) {
-	Name(_ADR, 0x00140007)
-} /* end SDCN */
-
-#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-
-/* 0:14.4 - PCI slot 1, 2, 3 */
-Device(PIBR) {
-	Name(_ADR, 0x00140004)
-	Name(_PRW, Package() {0x18, 4})
-
-	Method(_PRT, 0) {
-		Return (PCIB)
-	}
-}
-
-/* 0:14.6 - GEC Controller */
-Device(ACMD) {
-	Name(_ADR, 0x00140006)
-} /* end Ac97modem */
-#endif
-
-Name(CRES, ResourceTemplate() {
-	/* Set the Bus number and Secondary Bus number for the PCI0 device
-	 * The Secondary bus range for PCI0 lets the system
-	 * know what bus values are allowed on the downstream
-	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI buses can have 256 secondary buses which
-	 * range from [0-0xFF] but they do not need to be
-	 * sequential.
-	 */
-	WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-		0x0000,		/* address granularity */
-		0x0000,		/* range minimum */
-		0x00FF,		/* range maximum */
-		0x0000,		/* translation */
-		0x0100,		/* length */
-		,, PSB0)		/* ResourceSourceIndex, ResourceSource, DescriptorName */
-
-	IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
-
-	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000,		/* address granularity */
-		0x0000,		/* range minimum */
-		0x0CF7,		/* range maximum */
-		0x0000,		/* translation */
-		0x0CF8		/* length */
-	)
-	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000,		/* address granularity */
-		0x03B0,		/* range minimum */
-		0x03DF,		/* range maximum */
-		0x0000,		/* translation */
-		0x0030		/* length */
-	)
-
-	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000,		/* address granularity */
-		0x0D00,		/* range minimum */
-		0xFFFF,		/* range maximum */
-		0x0000,		/* translation */
-		0xF300		/* length */
-	)
-
-	Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)	/* VGA memory space */
-	Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
-
-	/* memory space for PCI BARs below 4GB */
-	Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
-}) /* End Name(_SB.PCI0.CRES) */
-
-Method(_CRS, 0) {
-	/* DBGO("\\_SB\\PCI0\\_CRS\n") */
-	CreateDWordField(CRES, ^MMIO._BAS, MM1B)
-	CreateDWordField(CRES, ^MMIO._LEN, MM1L)
-
-	/*
-	 * Declare memory between TOM1 and 4GB as available
-	 * for PCI MMIO.
-	 * Use ShiftLeft to avoid 64bit constant (for XP).
-	 * This will work even if the OS does 32bit arithmetic, as
-	 * 32bit (0x00000000 - TOM1) will wrap and give the same
-	 * result as 64bit (0x100000000 - TOM1).
-	 */
-	MM1B = TOM1
-	Local0 = 0x10000000 << 4
-	Local0 -= TOM1
-	MM1L = Local0
-
-	Return (CRES) /* note to change the Name buffer */
-} /* end of Method(_SB.PCI0._CRS) */
-
-#if CONFIG(HUDSON_IMC_FWM)
-	#include "acpi/AmdImc.asl" /* Hudson IMC function */
-#endif
-
-/*
- *
- *               FIRST METHOD CALLED UPON BOOT
- *
- *  1. If debugging, print current OS and ACPI interpreter.
- *  2. Get PCI Interrupt routing from ACPI VSM, this
- *     value is based on user choice in BIOS setup.
- */
-Method(_INI, 0) {
-	/* DBGO("\\_SB\\_INI\n") */
-	/* DBGO("   DSDT.ASL code from ") */
-	/* DBGO(__DATE__) */
-	/* DBGO(" ") */
-	/* DBGO(__TIME__) */
-	/* DBGO("\n   Sleep states supported: ") */
-	/* DBGO("\n") */
-	/* DBGO("   \\_OS=") */
-	/* DBGO(\_OS) */
-	/* DBGO("\n   \\_REV=") */
-	/* DBGO(\_REV) */
-	/* DBGO("\n") */
-
-#if CONFIG(HUDSON_IMC_FWM)
-#if CONFIG(ACPI_ENABLE_THERMAL_ZONE)
-	ITZE() /* enable IMC Fan Control*/
-#endif
-#endif
-} /* End Method(_SB._INI) */
diff --git a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl
deleted file mode 100644
index 6d723a99a3..0000000000
--- a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* 0:14.3 - LPC */
-Device(LIBR) {
-	Name(_ADR, 0x00140003)
-	/* Method(_INI) {
-	*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
-	} */ /* End Method(_SB.SBRDG._INI) */
-
-	OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
-	Field(CFG,DWordAcc,NoLock,Preserve){
-		Offset(0xA0),
-		BAR,32}		// SPI Controller Base Address Register (Index 0xA0)
-
-	Device(LDRC)	// LPC device: Resource consumption
-	{
-		Name (_HID, EISAID("PNP0C02"))  // ID for Motherboard resources
-		Name (CRS, ResourceTemplate ()  // Current Motherboard resources
-		{
-			Memory32Fixed(ReadWrite,	// Setup for fixed resource location for SPI base address
-			0x00000000,					// Address Base
-			0x00000000,					// Address Length
-			BAR0						// Descriptor Name
-			)
-		})
-
-		Method(_CRS,0,NotSerialized)
-		{
-			CreateDwordField(^CRS,^BAR0._BAS,SPIB)	// Field to hold SPI base address
-			CreateDwordField(^CRS,^BAR0._LEN,SPIL)	// Field to hold SPI address length
-			Store(BAR,SPIB)		// SPI base address mapped
-			Store(0x1000,SPIL)	// 4k space mapped
-			Return(CRS)
-		}
-	}
-
-	/* Real Time Clock Device */
-	Device(RTC0) {
-		Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
-		Name(_CRS, ResourceTemplate() {
-			IRQNoFlags(){8}
-			IO(Decode16,0x0070, 0x0070, 0, 2)
-		})
-	} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
-	Device(TMR) {	/* Timer */
-		Name(_HID,EISAID("PNP0100"))	/* System Timer */
-		Name(_CRS, ResourceTemplate() {
-			IRQNoFlags(){0}
-			IO(Decode16, 0x0040, 0x0040, 0, 4)
-		})
-	} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
-	Device(SPKR) {	/* Speaker */
-		Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
-		Name(_CRS, ResourceTemplate() {
-			IO(Decode16, 0x0061, 0x0061, 0, 1)
-		})
-	} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
-	Device(PIC) {
-		Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
-		Name(_CRS, ResourceTemplate() {
-			IRQNoFlags(){2}
-			IO(Decode16,0x0020, 0x0020, 0, 2)
-			IO(Decode16,0x00A0, 0x00A0, 0, 2)
-		})
-	} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
-	Device(MAD) { /* 8257 DMA */
-		Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
-		Name(_CRS, ResourceTemplate() {
-			DMA(Compatibility,BusMaster,Transfer8){4}
-			IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
-			IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
-			IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
-			IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
-			IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
-			IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
-		}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
-	} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
-	Device(COPR) {
-		Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
-		Name(_CRS, ResourceTemplate() {
-			IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
-			IRQNoFlags(){13}
-		})
-	} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-	#include "acpi/superio.asl"
-} /* end LIBR */
diff --git a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl
deleted file mode 100644
index 6ff81cd66f..0000000000
--- a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl
+++ /dev/null
@@ -1,442 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-	Field(PCFG, ByteAcc, NoLock, Preserve) {
-		/* Byte offsets are computed using the following technique:
-		 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
-		 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
-		*/
-		Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
-		STB5, 32,
-		Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
-		PT0D, 1,
-		PT1D, 1,
-		PT2D, 1,
-		PT3D, 1,
-		PT4D, 1,
-		PT5D, 1,
-		PT6D, 1,
-		PT7D, 1,
-		PT8D, 1,
-		PT9D, 1,
-		Offset(0x000A0004),	/* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
-		SBIE, 1,
-		SBME, 1,
-		Offset(0x000A0008),	/* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
-		SBRI, 8,
-		Offset(0x000A0014),	/* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
-		SBB1, 32,
-		Offset(0x000A0078),	/* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
-		,14,
-		P92E, 1,		/* Port92 decode enable */
-	}
-
-	OperationRegion(SB5, SystemMemory, STB5, 0x1000)
-		Field(SB5, AnyAcc, NoLock, Preserve){
-		/* Port 0 */
-		Offset(0x120),		/* Port 0 Task file status */
-		P0ER, 1,
-		, 2,
-		P0DQ, 1,
-		, 3,
-		P0BY, 1,
-		Offset(0x128),		/* Port 0 Serial ATA status */
-		P0DD, 4,
-		, 4,
-		P0IS, 4,
-		Offset(0x12C),		/* Port 0 Serial ATA control */
-		P0DI, 4,
-		Offset(0x130),		/* Port 0 Serial ATA error */
-		, 16,
-		P0PR, 1,
-
-		/* Port 1 */
-		offset(0x1A0),		/* Port 1 Task file status */
-		P1ER, 1,
-		, 2,
-		P1DQ, 1,
-		, 3,
-		P1BY, 1,
-		Offset(0x1A8),		/* Port 1 Serial ATA status */
-		P1DD, 4,
-		, 4,
-		P1IS, 4,
-		Offset(0x1AC),		/* Port 1 Serial ATA control */
-		P1DI, 4,
-		Offset(0x1B0),		/* Port 1 Serial ATA error */
-		, 16,
-		P1PR, 1,
-
-		/* Port 2 */
-		Offset(0x220),		/* Port 2 Task file status */
-		P2ER, 1,
-		, 2,
-		P2DQ, 1,
-		, 3,
-		P2BY, 1,
-		Offset(0x228),		/* Port 2 Serial ATA status */
-		P2DD, 4,
-		, 4,
-		P2IS, 4,
-		Offset(0x22C),		/* Port 2 Serial ATA control */
-		P2DI, 4,
-		Offset(0x230),		/* Port 2 Serial ATA error */
-		, 16,
-		P2PR, 1,
-
-		/* Port 3 */
-		Offset(0x2A0),		/* Port 3 Task file status */
-		P3ER, 1,
-		, 2,
-		P3DQ, 1,
-		, 3,
-		P3BY, 1,
-		Offset(0x2A8),		/* Port 3 Serial ATA status */
-		P3DD, 4,
-		, 4,
-		P3IS, 4,
-		Offset(0x2AC),		/* Port 3 Serial ATA control */
-		P3DI, 4,
-		Offset(0x2B0),		/* Port 3 Serial ATA error */
-		, 16,
-		P3PR, 1,
-	}
-
-	Name(IRQB, ResourceTemplate(){
-		IRQ(Level,ActiveLow,Shared){15}
-	})
-
-	Name(IRQP, ResourceTemplate(){
-		IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
-	})
-
-	Name(PITF, ResourceTemplate(){
-		IRQ(Level,ActiveLow,Exclusive){9}
-	})
-
-	Device(INTA) {
-		Name(_HID, EISAID("PNP0C0F"))
-		Name(_UID, 1)
-
-		Method(_STA, 0) {
-			if (PIRA) {
-				Return (0x0b) /* sata is invisible */
-			} else {
-				Return (0x09) /* sata is disabled */
-			}
-		} /* End Method(_SB.INTA._STA) */
-
-		Method(_DIS ,0) {
-			/* DBGO("\\_SB\\LNKA\\_DIS\n") */
-		} /* End Method(_SB.INTA._DIS) */
-
-		Method(_PRS ,0) {
-			/* DBGO("\\_SB\\LNKA\\_PRS\n") */
-			Return (IRQP)
-		} /* Method(_SB.INTA._PRS) */
-
-		Method(_CRS ,0) {
-			/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-			CreateWordField(IRQB, 0x1, IRQN)
-			IRQN = 1 << PIRA
-			Return (IRQB)
-		} /* Method(_SB.INTA._CRS) */
-
-		Method(_SRS, 1) {
-			/* DBGO("\\_SB\\LNKA\\_SRS\n") */
-			CreateWordField(ARG0, 1, IRQM)
-
-			/* Use lowest available IRQ */
-			FindSetRightBit(IRQM, Local0)
-			if (Local0) {
-				Local0--
-			}
-			PIRA = Local0
-		} /* End Method(_SB.INTA._SRS) */
-	} /* End Device(INTA) */
-
-	Device(INTB) {
-		Name(_HID, EISAID("PNP0C0F"))
-		Name(_UID, 2)
-
-		Method(_STA, 0) {
-			if (PIRB) {
-				Return (0x0b) /* sata is invisible */
-			} else {
-				Return (0x09) /* sata is disabled */
-			}
-		} /* End Method(_SB.INTB._STA) */
-
-		Method(_DIS ,0) {
-			/* DBGO("\\_SB\\LNKB\\_DIS\n") */
-		} /* End Method(_SB.INTB._DIS) */
-
-		Method(_PRS ,0) {
-			/* DBGO("\\_SB\\LNKB\\_PRS\n") */
-			Return (IRQP)
-		} /* Method(_SB.INTB._PRS) */
-
-		Method(_CRS ,0) {
-			/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-			CreateWordField(IRQB, 0x1, IRQN)
-			IRQN = 1 << PIRB
-			Return (IRQB)
-		} /* Method(_SB.INTB._CRS) */
-
-		Method(_SRS, 1) {
-			/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-			CreateWordField(ARG0, 1, IRQM)
-
-			/* Use lowest available IRQ */
-			FindSetRightBit(IRQM, Local0)
-			if (Local0) {
-				Local0--
-			}
-			PIRB = Local0
-		} /* End Method(_SB.INTB._SRS) */
-	} /* End Device(INTB)  */
-
-	Device(INTC) {
-		Name(_HID, EISAID("PNP0C0F"))
-		Name(_UID, 3)
-
-		Method(_STA, 0) {
-			if (PIRC) {
-				Return (0x0b) /* sata is invisible */
-			} else {
-				Return (0x09) /* sata is disabled */
-			}
-		} /* End Method(_SB.INTC._STA) */
-
-		Method(_DIS ,0) {
-			/* DBGO("\\_SB\\LNKC\\_DIS\n") */
-		} /* End Method(_SB.INTC._DIS) */
-
-		Method(_PRS ,0) {
-			/* DBGO("\\_SB\\LNKC\\_PRS\n") */
-			Return (IRQP)
-		} /* Method(_SB.INTC._PRS) */
-
-		Method(_CRS ,0) {
-			/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-			CreateWordField(IRQB, 0x1, IRQN)
-			IRQN = 1 << PIRC
-			Return (IRQB)
-		} /* Method(_SB.INTC._CRS) */
-
-		Method(_SRS, 1) {
-			/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-			CreateWordField(ARG0, 1, IRQM)
-
-			/* Use lowest available IRQ */
-			FindSetRightBit(IRQM, Local0)
-			if (Local0) {
-				Local0--
-			}
-			PIRC = Local0
-		} /* End Method(_SB.INTC._SRS) */
-	} /* End Device(INTC)  */
-
-	Device(INTD) {
-		Name(_HID, EISAID("PNP0C0F"))
-		Name(_UID, 4)
-
-		Method(_STA, 0) {
-			if (PIRD) {
-				Return (0x0b) /* sata is invisible */
-			} else {
-				Return (0x09) /* sata is disabled */
-			}
-		} /* End Method(_SB.INTD._STA) */
-
-		Method(_DIS ,0) {
-			/* DBGO("\\_SB\\LNKD\\_DIS\n") */
-		} /* End Method(_SB.INTD._DIS) */
-
-		Method(_PRS ,0) {
-			/* DBGO("\\_SB\\LNKD\\_PRS\n") */
-			Return (IRQP)
-		} /* Method(_SB.INTD._PRS) */
-
-		Method(_CRS ,0) {
-			/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-			CreateWordField(IRQB, 0x1, IRQN)
-			IRQN = 1 << PIRD
-			Return (IRQB)
-		} /* Method(_SB.INTD._CRS) */
-
-		Method(_SRS, 1) {
-			/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-			CreateWordField(ARG0, 1, IRQM)
-
-			/* Use lowest available IRQ */
-			FindSetRightBit(IRQM, Local0)
-			if (Local0) {
-				Local0--
-			}
-			PIRD = Local0
-		} /* End Method(_SB.INTD._SRS) */
-	} /* End Device(INTD)  */
-
-	Device(INTE) {
-		Name(_HID, EISAID("PNP0C0F"))
-		Name(_UID, 5)
-
-		Method(_STA, 0) {
-			if (PIRE) {
-				Return (0x0b) /* sata is invisible */
-			} else {
-				Return (0x09) /* sata is disabled */
-			}
-		} /* End Method(_SB.INTE._STA) */
-
-		Method(_DIS ,0) {
-			/* DBGO("\\_SB\\LNKE\\_DIS\n") */
-		} /* End Method(_SB.INTE._DIS) */
-
-		Method(_PRS ,0) {
-			/* DBGO("\\_SB\\LNKE\\_PRS\n") */
-			Return (IRQP)
-		} /* Method(_SB.INTE._PRS) */
-
-		Method(_CRS ,0) {
-			/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-			CreateWordField(IRQB, 0x1, IRQN)
-			IRQN = 1 << PIRE
-			Return (IRQB)
-		} /* Method(_SB.INTE._CRS) */
-
-		Method(_SRS, 1) {
-			/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-			CreateWordField(ARG0, 1, IRQM)
-
-			/* Use lowest available IRQ */
-			FindSetRightBit(IRQM, Local0)
-			if (Local0) {
-				Local0--
-			}
-			PIRE = Local0
-		} /* End Method(_SB.INTE._SRS) */
-	} /* End Device(INTE)  */
-
-	Device(INTF) {
-		Name(_HID, EISAID("PNP0C0F"))
-		Name(_UID, 6)
-
-		Method(_STA, 0) {
-			if (PIRF) {
-				Return (0x0b) /* sata is invisible */
-			} else {
-				Return (0x09) /* sata is disabled */
-			}
-		} /* End Method(_SB.INTF._STA) */
-
-		Method(_DIS ,0) {
-			/* DBGO("\\_SB\\LNKF\\_DIS\n") */
-		} /* End Method(_SB.INTF._DIS) */
-
-		Method(_PRS ,0) {
-			/* DBGO("\\_SB\\LNKF\\_PRS\n") */
-			Return (PITF)
-		} /* Method(_SB.INTF._PRS) */
-
-		Method(_CRS ,0) {
-			/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-			CreateWordField(IRQB, 0x1, IRQN)
-			IRQN = 1 << PIRF
-			Return (IRQB)
-		} /* Method(_SB.INTF._CRS) */
-
-		Method(_SRS, 1) {
-			/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-			CreateWordField(ARG0, 1, IRQM)
-
-			/* Use lowest available IRQ */
-			FindSetRightBit(IRQM, Local0)
-			if (Local0) {
-				Local0--
-			}
-			PIRF = Local0
-		} /*  End Method(_SB.INTF._SRS) */
-	} /* End Device(INTF)  */
-
-	Device(INTG) {
-		Name(_HID, EISAID("PNP0C0F"))
-		Name(_UID, 7)
-
-		Method(_STA, 0) {
-			if (PIRG) {
-				Return (0x0b) /* sata is invisible */
-			} else {
-				Return (0x09) /* sata is disabled */
-			}
-		} /* End Method(_SB.INTG._STA)  */
-
-		Method(_DIS ,0) {
-			/* DBGO("\\_SB\\LNKG\\_DIS\n") */
-		} /* End Method(_SB.INTG._DIS)  */
-
-		Method(_PRS ,0) {
-			/* DBGO("\\_SB\\LNKG\\_PRS\n") */
-			Return (IRQP)
-		} /* Method(_SB.INTG._CRS)  */
-
-		Method(_CRS ,0) {
-			/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-			CreateWordField(IRQB, 0x1, IRQN)
-			IRQN = 1 << PIRG
-			Return (IRQB)
-		} /* Method(_SB.INTG._CRS)  */
-
-		Method(_SRS, 1) {
-			/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-			CreateWordField(ARG0, 1, IRQM)
-
-			/* Use lowest available IRQ */
-			FindSetRightBit(IRQM, Local0)
-			if (Local0) {
-				Local0--
-			}
-			PIRG = Local0
-		} /* End Method(_SB.INTG._SRS)  */
-	} /* End Device(INTG)  */
-
-	Device(INTH) {
-		Name(_HID, EISAID("PNP0C0F"))
-		Name(_UID, 8)
-
-		Method(_STA, 0) {
-			if (PIRH) {
-				Return (0x0b) /* sata is invisible */
-			} else {
-				Return (0x09) /* sata is disabled */
-			}
-		} /* End Method(_SB.INTH._STA)  */
-
-		Method(_DIS ,0) {
-			/* DBGO("\\_SB\\LNKH\\_DIS\n") */
-		} /* End Method(_SB.INTH._DIS)  */
-
-		Method(_PRS ,0) {
-			/* DBGO("\\_SB\\LNKH\\_PRS\n") */
-			Return (IRQP)
-		} /* Method(_SB.INTH._CRS)  */
-
-		Method(_CRS ,0) {
-			/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-			CreateWordField(IRQB, 0x1, IRQN)
-			IRQN = 1 << PIRH
-			Return (IRQB)
-		} /* Method(_SB.INTH._CRS)  */
-
-		Method(_SRS, 1) {
-			/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-			CreateWordField(ARG0, 1, IRQM)
-
-			/* Use lowest available IRQ */
-			FindSetRightBit(IRQM, Local0)
-			if (Local0) {
-				Local0--
-			}
-			PIRH = Local0
-		} /* End Method(_SB.INTH._SRS)  */
-	} /* End Device(INTH)   */
diff --git a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl
deleted file mode 100644
index 294323fc0e..0000000000
--- a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-	/* PCI IRQ mapping registers, C00h-C01h. */
-	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
-		Field(PRQM, ByteAcc, NoLock, Preserve) {
-		PRQI, 0x00000008,
-		PRQD, 0x00000008,  /* Offset: 1h */
-	}
-	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
-		PIRA, 0x00000008,	/* Index 0 */
-		PIRB, 0x00000008,	/* Index 1 */
-		PIRC, 0x00000008,	/* Index 2 */
-		PIRD, 0x00000008,	/* Index 3 */
-		PIRE, 0x00000008,	/* Index 4 */
-		PIRF, 0x00000008,	/* Index 5 */
-		PIRG, 0x00000008,	/* Index 6 */
-		PIRH, 0x00000008,	/* Index 7 */
-	}
-
-	/* PCI Error control register */
-	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
-		Field(PERC, ByteAcc, NoLock, Preserve) {
-		SENS, 0x00000001,
-		PENS, 0x00000001,
-		SENE, 0x00000001,
-		PENE, 0x00000001,
-	}
-
-	/* Client Management index/data registers */
-	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
-		Field(CMT, ByteAcc, NoLock, Preserve) {
-		CMTI,	8,
-		/* Client Management Data register */
-		G64E,	1,
-		G64O,	1,
-		G32O,	2,
-		,		2,
-		GPSL,	2,
-	}
-
-	/* GPM Port register */
-	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
-		Field(GPT, ByteAcc, NoLock, Preserve) {
-		GPB0,1,
-		GPB1,1,
-		GPB2,1,
-		GPB3,1,
-		GPB4,1,
-		GPB5,1,
-		GPB6,1,
-		GPB7,1,
-	}
-
-	/* Flash ROM program enable register */
-	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
-		Field(FRE, ByteAcc, NoLock, Preserve) {
-		,     0x00000006,
-		FLRE, 0x00000001,
-	}
-
-	/* PM2 index/data registers */
-	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
-		Field(PM2R, ByteAcc, NoLock, Preserve) {
-		PM2I, 0x00000008,
-		PM2D, 0x00000008,
-	}
-
-	/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
-	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
-		Field(PIOR, ByteAcc, NoLock, Preserve) {
-		PIOI, 0x00000008,
-		PIOD, 0x00000008,
-	}
-
-	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
-		Offset(0xEE),
-		UPWS, 3,
-	}
diff --git a/src/southbridge/amd/agesa/hudson/acpi/smbus.asl b/src/southbridge/amd/agesa/hudson/acpi/smbus.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/southbridge/amd/agesa/hudson/acpi/smbus.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/southbridge/amd/agesa/hudson/acpi/usb.asl b/src/southbridge/amd/agesa/hudson/acpi/usb.asl
deleted file mode 100644
index 399ce6eecb..0000000000
--- a/src/southbridge/amd/agesa/hudson/acpi/usb.asl
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* 0:12.0 - OHCI */
-Device(UOH1) {
-	Name(_ADR, 0x00120000)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH1 */
-
-/* 0:12.2 - EHCI */
-Device(UOH2) {
-	Name(_ADR, 0x00120002)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH2 */
-
-/* 0:13.0 - OHCI */
-Device(UOH3) {
-	Name(_ADR, 0x00130000)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH3 */
-
-/* 0:13.2 - EHCI */
-Device(UOH4) {
-	Name(_ADR, 0x00130002)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH4 */
-
-/* 0:16.0 - OHCI */
-Device(UOH5) {
-	Name(_ADR, 0x00160000)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH5 */
-
-/* 0:16.2 - EHCI */
-Device(UOH6) {
-	Name(_ADR, 0x00160002)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH5 */
-
-#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-/* 0:14.5 - OHCI */
-Device(UEH1) {
-	Name(_ADR, 0x00140005)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UEH1 */
-#endif
-
-/* 0:10.0 - XHCI 0*/
-Device(XHC0) {
-	Name(_ADR, 0x00100000)
-	Name(_PRW, Package() {0x0B, 4})
-} /* end XHC0 */
-
-#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-/* 0:10.1 - XHCI 1*/
-Device(XHC1) {
-	Name(_ADR, 0x00100001)
-	Name(_PRW, Package() {0x0B, 4})
-} /* end XHC1 */
-#endif
diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
deleted file mode 100644
index 20c15f0cdd..0000000000
--- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_PCI_INT_DEFS_H
-#define AMD_PCI_INT_DEFS_H
-
-/*
- * PIRQ and device routing - these define the index
- * into the FCH PCI_INTR 0xC00/0xC01 interrupt
- * routing table
- */
-#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
-#define FCH_INT_TABLE_SIZE 0x54
-#elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-#define FCH_INT_TABLE_SIZE 0x42
-#endif
-
-#define PIRQ_NC		0x1F	/* Not Used */
-#define PIRQ_A		0x00	/* INT A */
-#define PIRQ_B		0x01	/* INT B */
-#define PIRQ_C		0x02	/* INT C */
-#define PIRQ_D		0x03	/* INT D */
-#define PIRQ_E		0x04	/* INT E */
-#define PIRQ_F		0x05	/* INT F */
-#define PIRQ_G		0x06	/* INT G */
-#define PIRQ_H		0x07	/* INT H */
-#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings - See FCH Spec */
-#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
-#define PIRQ_MISC1	0x0A	/* Miscellaneous1 IRQ Settings */
-#define PIRQ_MISC2	0x0B	/* Miscellaneous2 IRQ Settings */
-#define PIRQ_SIRQA	0x0C	/* Serial IRQ INTA */
-#define PIRQ_SIRQB	0x0D	/* Serial IRQ INTB */
-#define PIRQ_SIRQC	0x0E	/* Serial IRQ INTC */
-#define PIRQ_SIRQD	0x0F	/* Serial IRQ INTD */
-#define PIRQ_SCI	0x10	/* SCI IRQ */
-#define PIRQ_SMBUS	0x11	/* SMBUS	14h.0 */
-#define PIRQ_ASF	0x12	/* ASF */
-#define PIRQ_HDA	0x13	/* HDA		14h.2 */
-#define PIRQ_FC		0x14	/* FC */
-#define PIRQ_GEC	0x15	/* GEC */
-#define PIRQ_PMON	0x16	/* Performance Monitor */
-#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-#define PIRQ_SD		0x17	/* SD */
-#endif
-#define PIRQ_IMC0	0x20	/* IMC INT0 */
-#define PIRQ_IMC1	0x21	/* IMC INT1 */
-#define PIRQ_IMC2	0x22	/* IMC INT2 */
-#define PIRQ_IMC3	0x23	/* IMC INT3 */
-#define PIRQ_IMC4	0x24	/* IMC INT4 */
-#define PIRQ_IMC5	0x25	/* IMC INT5 */
-#define PIRQ_OHCI1	0x30	/* USB OHCI	12h.0 */
-#define PIRQ_EHCI1	0x31	/* USB EHCI	12h.2 */
-#define PIRQ_OHCI2	0x32	/* USB OHCI	13h.0 */
-#define PIRQ_EHCI2	0x33	/* USB EHCI	13h.2 */
-#define PIRQ_OHCI3	0x34	/* USB OHCI	16h.0 */
-#define PIRQ_EHCI3	0x35	/* USB EHCI	16h.2 */
-#define PIRQ_OHCI4	0x36	/* USB OHCI	14h.5 */
-#define PIRQ_IDE	0x40	/* IDE		14h.1 */
-#define PIRQ_SATA	0x41	/* SATA		11h.0 */
-#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
-#define PIRQ_SD		0x42	/* SD		14h.7 */
-#define PIRQ_GPP0	0x50	/* GPP INT 0 */
-#define PIRQ_GPP1	0x51	/* GPP INT 1 */
-#define PIRQ_GPP2	0x52	/* GPP INT 2 */
-#define PIRQ_GPP3	0x53	/* GPP INT 3 */
-#endif
-
-#endif /* AMD_PCI_INT_DEFS_H */
diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
deleted file mode 100644
index 46200eaad4..0000000000
--- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_PCI_INT_TYPES_H
-#define AMD_PCI_INT_TYPES_H
-
-#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
-const char *intr_types[] = {
-	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
-	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
-	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t",
-	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
-	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
-	[0x40] = "IDE\t", "SATA\t",
-	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"
-};
-#elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-const char *intr_types[] = {
-	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
-	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
-	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t",
-	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
-	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB",
-	[0x40] = "RSVD\t", "SATA\t",
-};
-#endif
-
-#endif /* AMD_PCI_INT_TYPES_H */
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
deleted file mode 100644
index 039712fca6..0000000000
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <stdint.h>
-#include <arch/bootblock.h>
-#include <amdblocks/acpimmio.h>
-#include <device/pci_ops.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-/*
- * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
- *
- * Hardware should enable LPC ROM by pin straps. This function does not
- * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
- *
- * The HUDSON power-on default is to map 512K ROM space.
- *
- */
-static void hudson_enable_rom(void)
-{
-	u8 reg8;
-	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
-
-	/* Decode variable LPC ROM address ranges 1 and 2. */
-	reg8 = pci_s_read_config8(dev, 0x48);
-	reg8 |= (1 << 3) | (1 << 4);
-	pci_s_write_config8(dev, 0x48, reg8);
-
-	/* LPC ROM address range 1: */
-	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
-	pci_s_write_config16(dev, 0x68, 0x000e);
-	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
-	pci_s_write_config16(dev, 0x6a, 0x000f);
-
-	/* LPC ROM address range 2: */
-	/*
-	 * Enable LPC ROM range start at:
-	 * 0xfff8(0000): 512KB
-	 * 0xfff0(0000): 1MB
-	 * 0xffe0(0000): 2MB
-	 * 0xffc0(0000): 4MB
-	 */
-	pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
-	/* Enable LPC ROM range end at 0xffff(ffff). */
-	pci_s_write_config16(dev, 0x6e, 0xffff);
-}
-
-void bootblock_early_southbridge_init(void)
-{
-	u32 data;
-
-	hudson_enable_rom();
-	enable_acpimmio_decode_pm24();
-	hudson_lpc_decode();
-
-	if (CONFIG(POST_DEVICE_PCI_PCIE))
-		hudson_pci_port80();
-	else if (CONFIG(POST_DEVICE_LPC))
-		hudson_lpc_port80();
-
-	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
-	data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
-	/* enable 0x2e/0x4e IO decoding for SuperIO */
-	pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
-
-	/*
-	 * Enable FCH to decode TPM associated Memory and IO regions for vboot
-	 *
-	 * Enable decoding of TPM cycles defined in TPM 1.2 spec
-	 * Enable decoding of legacy TPM addresses: IO addresses 0x7f-
-	 * 0x7e and 0xef-0xee.
-	 */
-	data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE);
-	data |= TPM_12_EN | TPM_LEGACY_EN;
-	pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data);
-
-	/*
-	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
-	 *  LpcClk[1:0]".  This following register setting has been
-	 *  replicated in every reference design since Parmer, so it is
-	 *  believed to be required even though it is not documented in
-	 *  the SoC BKDGs.  Without this setting, there is no serial
-	 *  output.
-	 */
-	pm_write8(0xd2, 0);
-}
diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h
deleted file mode 100644
index 6eba9f2063..0000000000
--- a/src/southbridge/amd/agesa/hudson/chip.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef HUDSON_CHIP_H
-#define HUDSON_CHIP_H
-
-struct southbridge_amd_agesa_hudson_config
-{
-	u8  sd_mode;
-};
-
-#endif /* HUDSON_CHIP_H */
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
deleted file mode 100644
index 18bc9b22d2..0000000000
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _HUDSON_EARLY_SETUP_C_
-#define _HUDSON_EARLY_SETUP_C_
-
-#include <stdint.h>
-#include <amdblocks/acpimmio.h>
-#include <device/pci_ops.h>
-
-#include "hudson.h"
-
-void hudson_pci_port80(void)
-{
-	u8 byte;
-	pci_devfn_t dev;
-
-	/* P2P Bridge */
-	dev = PCI_DEV(0, 0x14, 4);
-
-	/* Chip Control: Enable subtractive decoding */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 5;
-	pci_write_config8(dev, 0x40, byte);
-
-	/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 7;
-	pci_write_config8(dev, 0x4B, byte);
-
-	/* The same IO Base and IO Limit here is meaningful because we set the
-	 * bridge to be subtractive. During early setup stage, we have to make
-	 * sure that data can go through port 0x80.
-	 */
-	/* IO Base: 0xf000 */
-	byte = pci_read_config8(dev, 0x1C);
-	byte |= 0xF << 4;
-	pci_write_config8(dev, 0x1C, byte);
-
-	/* IO Limit: 0xf000 */
-	byte = pci_read_config8(dev, 0x1D);
-	byte |= 0xF << 4;
-	pci_write_config8(dev, 0x1D, byte);
-
-	/* PCI Command: Enable IO response */
-	byte = pci_read_config8(dev, 0x04);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x04, byte);
-
-	/* LPC controller */
-	dev = PCI_DEV(0, 0x14, 3);
-
-	byte = pci_read_config8(dev, 0x4A);
-	byte &= ~(1 << 5); /* disable lpc port 80 */
-	pci_write_config8(dev, 0x4A, byte);
-}
-
-void hudson_lpc_port80(void)
-{
-	u8 byte;
-
-	/* Enable port 80 LPC decode in pci function 3 configuration space. */
-	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
-	byte = pci_read_config8(dev, 0x4a);
-	byte |= 1 << 5; /* enable port 80 */
-	pci_write_config8(dev, 0x4a, byte);
-}
-
-void hudson_lpc_decode(void)
-{
-	u32 tmp;
-
-	/* Enable LPC controller */
-	pm_write8(0xec, pm_read8(0xec) | 0x01);
-
-	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
-	/* Serial port enumeration on Hudson:
-	 * PORT0 - 0x3f8
-	 * PORT1 - 0x2f8
-	 * PORT5 - 0x2e8
-	 * PORT7 - 0x3e8
-	 */
-	tmp =  DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1
-	     | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7;
-
-	pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp);
-}
-
-#endif /* _HUDSON_EARLY_SETUP_C_ */
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
deleted file mode 100644
index 9dda666fe1..0000000000
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <device/mmio.h>
-#include <device/pci_ehci.h>
-#include <device/pci_def.h>
-#include "hudson.h"
-
-#define DEBUGPORT_MISC_CONTROL		0x80
-
-pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
-{
-	/* Enable all of the USB controllers */
-	outb(0xEF, PM_INDEX);
-	outb(0x7F, PM_DATA);
-
-	if (hcd_idx == 3)
-		return PCI_DEV(0, 0x16, 2);
-	else if (hcd_idx == 2)
-		return PCI_DEV(0, 0x13, 2);
-	else
-		return PCI_DEV(0, 0x12, 2);
-}
-
-void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
-{
-	u8 *base_regs = pci_ehci_base_regs(dev);
-	u32 reg32;
-
-	/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
-	reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
-	reg32 &= ~(0xf << 28);
-	reg32 |= (port << 28);
-	reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
-	write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
-}
diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c
deleted file mode 100644
index 2b39bcd043..0000000000
--- a/src/southbridge/amd/agesa/hudson/fadt.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <console/console.h>
-#include <acpi/acpi.h>
-#include <device/device.h>
-#include <version.h>
-
-#include "hudson.h"
-#include "smi.h"
-
-#if CONFIG(HUDSON_LEGACY_FREE)
-	#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
-#else
-	#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
-#endif
-
-/*
- * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
- * in the ACPI 3.0b specification.
- */
-void acpi_fill_fadt(acpi_fadt_t *fadt)
-{
-	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", HUDSON_ACPI_IO_BASE);
-
-	fadt->sci_int = 9;		/* HUDSON - IRQ 09 - ACPI SCI */
-
-	if (permanent_smi_handler()) {
-		fadt->smi_cmd = ACPI_SMI_CTL_PORT;
-		fadt->acpi_enable = ACPI_SMI_CMD_ENABLE;
-		fadt->acpi_disable = ACPI_SMI_CMD_DISABLE;
-	}
-
-	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
-	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
-	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
-	fadt->gpe0_blk = ACPI_GPE0_BLK;
-
-	fadt->pm1_evt_len = 4;	/* 32 bits */
-	fadt->pm1_cnt_len = 2;	/* 16 bits */
-	fadt->pm_tmr_len = 4;	/* 32 bits */
-	fadt->gpe0_blk_len = 8;	/* 64 bits */
-
-	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
-	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
-	fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */
-	fadt->duty_width = 3;	/* CLK_VAL bits 3:1 */
-	fadt->day_alrm = 0;	/* 0x7d these have to be */
-	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->iapc_boot_arch = FADT_BOOT_ARCH;	/* See table 5-10 */
-	fadt->res2 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
-	fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
-				ACPI_FADT_C1_SUPPORTED |
-				ACPI_FADT_SLEEP_BUTTON |
-				ACPI_FADT_S4_RTC_WAKE |
-				ACPI_FADT_32BIT_TIMER |
-				ACPI_FADT_PCI_EXPRESS_WAKE |
-				ACPI_FADT_PLATFORM_CLOCK |
-				ACPI_FADT_S4_RTC_VALID |
-				ACPI_FADT_REMOTE_POWER_ON;
-
-	fadt->ARM_boot_arch = 0;	/* Must be zero if ACPI Revision <= 5.0 */
-
-	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
-	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED;
-	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
-	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; /* EventStatus + Event Enable */
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
-	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
-	fadt->x_gpe0_blk.addrh = 0x0;
-}
diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c
deleted file mode 100644
index a63d52a8d2..0000000000
--- a/src/southbridge/amd/agesa/hudson/hda.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-#include "hudson.h"
-
-static void hda_init(struct device *dev)
-{
-}
-
-static struct device_operations hda_audio_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = hda_init,
-	.ops_pci = &pci_dev_ops_pci,
-};
-
-static const struct pci_driver hdaaudio_driver __pci_driver = {
-	.ops = &hda_audio_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_HDA,
-};
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
deleted file mode 100644
index 0c96ec15a3..0000000000
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <console/console.h>
-#include <device/mmio.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <types.h>
-
-#include "hudson.h"
-#include "imc.h"
-#include "smbus.h"
-#include "smi.h"
-
-#define PM_REG_USB_ENABLE	0xef
-
-enum usb_enable {
-	USB_EN_DEVFN_12_0 = (1 << 0),
-	USB_EN_DEVFN_12_2 = (1 << 1),
-	USB_EN_DEVFN_13_0 = (1 << 2),
-	USB_EN_DEVFN_13_2 = (1 << 3),
-	USB_EN_DEVFN_16_0 = (1 << 4),
-	USB_EN_DEVFN_16_2 = (1 << 5),
-};
-
-static void hudson_disable_usb(u8 disable)
-{
-	u8 reg8;
-
-	/* Bit 7 handles routing, 6 is reserved. we don't mess with those */
-	disable &= 0x3f;
-
-	reg8 = pm_read8(PM_REG_USB_ENABLE);
-	reg8 &= ~disable;
-	pm_write8(PM_REG_USB_ENABLE, reg8);
-}
-
-void hudson_enable(struct device *dev)
-{
-	printk(BIOS_DEBUG, "%s()\n", __func__);
-	switch (dev->path.pci.devfn) {
-	case PCI_DEVFN(0x14, 5):
-		if (dev->enabled == 0) {
-			u32 usb_device_id = pci_read_config16(dev, PCI_DEVICE_ID);
-			u8 reg8;
-			if (usb_device_id == PCI_DID_AMD_SB900_USB_20_5) {
-				/* turn off and remove device 0:14.5 from PCI space */
-				reg8 = pm_read8(0xef);
-				reg8 &= ~BIT(6);
-				pm_write8(0xef, reg8);
-			}
-		}
-		break;
-
-	case PCI_DEVFN(0x14, 7):
-		if (dev->enabled == 0) {
-			u32 sd_device_id = pci_read_config16(dev, PCI_DEVICE_ID);
-			/* turn off the SDHC controller in the PM reg */
-			u8 reg8;
-			if (sd_device_id == PCI_DID_AMD_HUDSON_SD) {
-				reg8 = pm_read8(0xe7);
-				reg8 &= ~BIT(0);
-				pm_write8(0xe7, reg8);
-			} else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
-				reg8 = pm_read8(0xe8);
-				reg8 &= ~BIT(0);
-				pm_write8(0xe8, reg8);
-			}
-			/* remove device 0:14.7 from PCI space */
-			reg8 = pm_read8(0xd3);
-			reg8 &= ~BIT(6);
-			pm_write8(0xd3, reg8);
-		}
-		break;
-
-	/* Make sure to disable other functions if function 0 is disabled */
-	case PCI_DEVFN(0x12, 0):
-		if (dev->enabled == 0)
-			hudson_disable_usb(USB_EN_DEVFN_12_0);
-		__fallthrough;
-	case PCI_DEVFN(0x12, 2):
-		if (dev->enabled == 0)
-			hudson_disable_usb(USB_EN_DEVFN_12_2);
-		break;
-	case PCI_DEVFN(0x13, 0):
-		if (dev->enabled == 0)
-			hudson_disable_usb(USB_EN_DEVFN_13_0);
-		__fallthrough;
-	case PCI_DEVFN(0x13, 2):
-		if (dev->enabled == 0)
-			hudson_disable_usb(USB_EN_DEVFN_13_2);
-		break;
-	case PCI_DEVFN(0x16, 0):
-		if (dev->enabled == 0)
-			hudson_disable_usb(USB_EN_DEVFN_16_0);
-		__fallthrough;
-	case PCI_DEVFN(0x16, 2):
-		if (dev->enabled == 0)
-			hudson_disable_usb(USB_EN_DEVFN_16_2);
-		break;
-	default:
-		break;
-	}
-}
-
-static void hudson_init_acpi_ports(void)
-{
-	/* We use some of these ports in SMM regardless of whether or not
-	 * ACPI tables are generated. Enable these ports indiscriminately.
-	 */
-
-	pm_write16(0x60, ACPI_PM_EVT_BLK);
-	pm_write16(0x62, ACPI_PM1_CNT_BLK);
-	pm_write16(0x64, ACPI_PM_TMR_BLK);
-	pm_write16(0x68, ACPI_GPE0_BLK);
-	/* CpuControl is in \_PR.CP00, 6 bytes */
-	pm_write16(0x66, ACPI_CPU_CONTROL);
-
-	if (CONFIG(HAVE_SMI_HANDLER)) {
-		pm_write16(0x6a, ACPI_SMI_CTL_PORT);
-		hudson_enable_acpi_cmd_smi();
-	} else {
-		pm_write16(0x6a, 0);
-	}
-
-	/* AcpiDecodeEnable, When set, SB uses the contents of the PM registers
-	 * at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn
-	 */
-	pm_write8(0x74, BIT(0) | BIT(1) | BIT(4) | BIT(2));
-}
-
-static void hudson_init(void *chip_info)
-{
-	hudson_init_acpi_ports();
-}
-
-static void hudson_final(void *chip_info)
-{
-	/* AMD AGESA does not enable thermal zone, so we enable it here. */
-	if (CONFIG(HUDSON_IMC_FWM) && !CONFIG(ACPI_ENABLE_THERMAL_ZONE))
-		enable_imc_thermal_zone();
-}
-
-struct chip_operations southbridge_amd_agesa_hudson_ops = {
-	CHIP_NAME("ATI HUDSON")
-	.enable_dev = hudson_enable,
-	.init = hudson_init,
-	.final = hudson_final
-};
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h
deleted file mode 100644
index eeb60ca35a..0000000000
--- a/src/southbridge/amd/agesa/hudson/hudson.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef HUDSON_H
-#define HUDSON_H
-
-#include <device/device.h>
-#include <types.h>
-
-/* Power management index/data registers */
-#define BIOSRAM_INDEX	0xcd4
-#define BIOSRAM_DATA	0xcd5
-#define PM_INDEX	0xcd6
-#define PM_DATA		0xcd7
-#define PM2_INDEX	0xcd0
-#define PM2_DATA	0xcd1
-
-#define HUDSON_ACPI_IO_BASE 0x800
-
-#define ACPI_PM_EVT_BLK		(HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK	(HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */
-#define ACPI_PM_TMR_BLK		(HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK		(HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTROL	(HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */
-
-#define ACPI_SMI_CTL_PORT		0xb2
-#define ACPI_SMI_CMD_CST_CONTROL	0xde
-#define ACPI_SMI_CMD_PST_CONTROL	0xad
-#define ACPI_SMI_CMD_DISABLE		0xbe
-#define ACPI_SMI_CMD_ENABLE		0xef
-#define ACPI_SMI_CMD_S4_REQ		0xc0
-
-#define REV_HUDSON_A11	0x11
-#define REV_HUDSON_A12	0x12
-
-#define LPC_IO_PORT_DECODE_ENABLE	0x44
-#define   DECODE_ENABLE_PARALLEL_PORT0	BIT(0)
-#define   DECODE_ENABLE_PARALLEL_PORT1	BIT(1)
-#define   DECODE_ENABLE_PARALLEL_PORT2	BIT(2)
-#define   DECODE_ENABLE_PARALLEL_PORT3	BIT(3)
-#define   DECODE_ENABLE_PARALLEL_PORT4	BIT(4)
-#define   DECODE_ENABLE_PARALLEL_PORT5	BIT(5)
-#define   DECODE_ENABLE_SERIAL_PORT0	BIT(6)
-#define   DECODE_ENABLE_SERIAL_PORT1	BIT(7)
-#define   DECODE_ENABLE_SERIAL_PORT2	BIT(8)
-#define   DECODE_ENABLE_SERIAL_PORT3	BIT(9)
-#define   DECODE_ENABLE_SERIAL_PORT4	BIT(10)
-#define   DECODE_ENABLE_SERIAL_PORT5	BIT(11)
-#define   DECODE_ENABLE_SERIAL_PORT6	BIT(12)
-#define   DECODE_ENABLE_SERIAL_PORT7	BIT(13)
-#define   DECODE_ENABLE_AUDIO_PORT0	BIT(14)
-#define   DECODE_ENABLE_AUDIO_PORT1	BIT(15)
-#define   DECODE_ENABLE_AUDIO_PORT2	BIT(16)
-#define   DECODE_ENABLE_AUDIO_PORT3	BIT(17)
-#define   DECODE_ENABLE_MIDI_PORT0	BIT(18)
-#define   DECODE_ENABLE_MIDI_PORT1	BIT(19)
-#define   DECODE_ENABLE_MIDI_PORT2	BIT(20)
-#define   DECODE_ENABLE_MIDI_PORT3	BIT(21)
-#define   DECODE_ENABLE_MSS_PORT0	BIT(22)
-#define   DECODE_ENABLE_MSS_PORT1	BIT(23)
-#define   DECODE_ENABLE_MSS_PORT2	BIT(24)
-#define   DECODE_ENABLE_MSS_PORT3	BIT(25)
-#define   DECODE_ENABLE_FDC_PORT0	BIT(26)
-#define   DECODE_ENABLE_FDC_PORT1	BIT(27)
-#define   DECODE_ENABLE_GAME_PORT	BIT(28)
-#define   DECODE_ENABLE_KBC_PORT	BIT(29)
-#define   DECODE_ENABLE_ACPIUC_PORT	BIT(30)
-#define   DECODE_ENABLE_ADLIB_PORT	BIT(31)
-
-#define LPC_IO_OR_MEM_DECODE_ENABLE	0x48
-
-#define LPC_TRUSTED_PLATFORM_MODULE	0x7c
-#define   TPM_12_EN			BIT(0)
-#define   TPM_LEGACY_EN			BIT(2)
-
-#define SPIROM_BASE_ADDRESS_REGISTER  0xA0
-#define SPI_ROM_ENABLE                0x02
-#define SPI_BASE_ADDRESS              0xFEC10000
-
-static inline int hudson_sata_enable(void)
-{
-	/* True if IDE or AHCI. */
-	return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2);
-}
-
-static inline int hudson_ide_enable(void)
-{
-	/* True if IDE or LEGACY IDE. */
-	return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3);
-}
-
-void hudson_lpc_port80(void);
-void hudson_pci_port80(void);
-void hudson_lpc_decode(void);
-void hudson_clk_output_48Mhz(void);
-
-void hudson_enable(struct device *dev);
-
-#endif /* HUDSON_H */
diff --git a/src/southbridge/amd/agesa/hudson/ide.c b/src/southbridge/amd/agesa/hudson/ide.c
deleted file mode 100644
index eaf40b5888..0000000000
--- a/src/southbridge/amd/agesa/hudson/ide.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "hudson.h"
-
-static void ide_init(struct device *dev)
-{
-}
-
-static struct device_operations ide_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = ide_init,
-	.ops_pci = &pci_dev_ops_pci,
-};
-
-static const struct pci_driver ide_driver __pci_driver = {
-	.ops = &ide_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_IDE,
-};
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
deleted file mode 100644
index b1a71f3f32..0000000000
--- a/src/southbridge/amd/agesa/hudson/imc.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include "imc.h"
-#include <amdblocks/acpimmio.h>
-#include <device/mmio.h>
-#include <Porting.h>
-#include <AGESA.h>
-#include <amdlib.h>
-#include <Proc/Fch/Fch.h>
-#include <Proc/Fch/Common/FchCommonCfg.h>
-#include <Proc/Fch/FchPlatform.h>
-
-void imc_reg_init(void)
-{
-	/* Init Power Management Block 2 (PM2) Registers.
-	 * Check BKDG for AMD Family 16h for details. */
-	pm2_write8(0, 0x06);
-	pm2_write8(1, 0x06);
-	pm2_write8(2, 0xf7);
-	pm2_write8(3, 0xff);
-	pm2_write8(4, 0xff);
-
-#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-	pm2_write8(0x10, 0x06);
-	pm2_write8(0x11, 0x06);
-	pm2_write8(0x12, 0xf7);
-	pm2_write8(0x13, 0xff);
-	pm2_write8(0x14, 0xff);
-#endif
-
-#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-	UINT8 PciData;
-	PCI_ADDR PciAddress;
-	AMD_CONFIG_PARAMS StdHeader;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0x3, 0x1E4);
-	LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
-	PciData &= (UINT8)0x8F;
-	PciData |= 0x10;
-	LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
-#endif
-}
-
-void enable_imc_thermal_zone(void)
-{
-	AMD_CONFIG_PARAMS StdHeader;
-	UINT8 FunNum;
-	UINT8 regs[10];
-	int i;
-
-	regs[0] = 0;
-	regs[1] = 0;
-	FunNum = Fun_80;
-	for (i = 0; i <= 1; i++)
-		WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
-	WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader);     // function number
-	WaitForEcLDN9MailboxCmdAck(&StdHeader);
-
-	for (i = 2; i < ARRAY_SIZE(regs); i++)
-		ReadECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
-
-	/* enable thermal zone 0 */
-	regs[2] |= 1;
-	regs[0] = 0;
-	regs[1] = 0;
-	FunNum = Fun_81;
-	for (i = 0; i < ARRAY_SIZE(regs); i++)
-		WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
-	WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader);     // function number
-	WaitForEcLDN9MailboxCmdAck(&StdHeader);
-}
diff --git a/src/southbridge/amd/agesa/hudson/imc.h b/src/southbridge/amd/agesa/hudson/imc.h
deleted file mode 100644
index 29e7fd79b6..0000000000
--- a/src/southbridge/amd/agesa/hudson/imc.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef HUDSON_IMC_H
-#define HUDSON_IMC_H
-
-void imc_reg_init(void);
-void enable_imc_thermal_zone(void);
-
-#endif
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
deleted file mode 100644
index 2efc5bc2a5..0000000000
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pnp.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/isa-dma.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <acpi/acpi.h>
-#include <pc80/i8254.h>
-#include <pc80/i8259.h>
-#include "hudson.h"
-#include "pci_devs.h"
-
-static void lpc_init(struct device *dev)
-{
-	u8 byte;
-	u32 dword;
-	struct device *sm_dev;
-
-	/* Enable the LPC Controller */
-	sm_dev = pcidev_on_root(0x14, 0);
-	dword = pci_read_config32(sm_dev, 0x64);
-	dword |= 1 << 20;
-	pci_write_config32(sm_dev, 0x64, dword);
-
-	/* Initialize isa dma */
-	isa_dma_init();
-
-	/* Enable DMA transaction on the LPC bus */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 2);
-	pci_write_config8(dev, 0x40, byte);
-
-	/* Disable the timeout mechanism on LPC */
-	byte = pci_read_config8(dev, 0x48);
-	byte &= ~(1 << 7);
-	pci_write_config8(dev, 0x48, byte);
-
-	/* Disable LPC MSI Capability */
-	byte = pci_read_config8(dev, 0x78);
-	byte &= ~(1 << 1);
-	byte &= ~(1 << 0);	/* Keep the old way. i.e., when bus master/DMA cycle is going
-				   on on LPC, it holds PCI grant, so no LPC slave cycle can
-				   interrupt and visit LPC. */
-	pci_write_config8(dev, 0x78, byte);
-
-	/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
-	/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
-	byte = pci_read_config8(dev, 0xBB);
-	byte |= 1 << 0 | 1 << 3;
-	pci_write_config8(dev, 0xBB, byte);
-
-	cmos_check_update_date();
-
-	/*
-	 * Initialize the real time clock.
-	 * The 0 argument tells cmos_init not to
-	 * update CMOS unless it is invalid.
-	 * 1 tells cmos_init to always initialize the CMOS.
-	 */
-	cmos_init(0);
-
-	/* Initialize i8259 pic */
-	setup_i8259();
-
-	/* Initialize i8254 timers */
-	setup_i8254();
-}
-
-static void hudson_lpc_read_resources(struct device *dev)
-{
-	struct resource *res;
-
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
-
-	/* Add an extra subtractive resource for both memory and I/O. */
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->base = 0;
-	res->size = 0x1000;
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->base = 0xff800000;
-	res->size = 0x00800000; /* 8 MB for flash */
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	/* Add a memory resource for the SPI BAR. */
-	mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB);
-
-	res = new_resource(dev, 3); /* IOAPIC */
-	res->base = IO_APIC_ADDR;
-	res->size = 0x00001000;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	compact_resources(dev);
-}
-
-static void hudson_lpc_set_resources(struct device *dev)
-{
-	struct resource *res;
-
-	/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
-	res = find_resource(dev, 2);
-	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
-
-	pci_dev_set_resources(dev);
-}
-
-/**
- * @brief Enable resources for children devices
- *
- * @param dev the device whose children's resources are to be enabled
- *
- */
-static void hudson_lpc_enable_childrens_resources(struct device *dev)
-{
-	struct bus *link;
-	u32 reg, reg_x;
-	int var_num = 0;
-	u16 reg_var[3];
-	u16 reg_size[1] =  {512};
-	u8 wiosize = pci_read_config8(dev, 0x74);
-
-	/* Be bit relaxed, tolerate that LPC region might be bigger than resource we try to fit,
-	 * do it like this for all regions < 16 bytes. If there is a resource > 16 bytes
-	 * it must be 512 bytes to be able to allocate the fresh LPC window.
-	 *
-	 * AGESA likes to enable already one LPC region in wide port base 0x64-0x65,
-	 * using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size
-	 * The code tries to check if resource can fit into this region
-	 */
-
-	reg = pci_read_config32(dev, 0x44);
-	reg_x = pci_read_config32(dev, 0x48);
-
-	/* check if ranges are free and not use them if entry is just already taken */
-	if (reg_x & (1 << 2))
-		var_num = 1;
-	/* just in case check if someone did not manually set other ranges too */
-	if (reg_x & (1 << 24))
-		var_num = 2;
-
-	if (reg_x & (1 << 25))
-		var_num = 3;
-
-	/* check AGESA region size */
-	if (wiosize & (1 << 0))
-		reg_size[0] = 16;
-
-	reg_var[2] = pci_read_config16(dev, 0x90);
-	reg_var[1] = pci_read_config16(dev, 0x66);
-	reg_var[0] = pci_read_config16(dev, 0x64);
-
-	for (link = dev->link_list; link; link = link->next) {
-		struct device *child;
-		for (child = link->children; child;
-		     child = child->sibling) {
-			if (child->enabled
-			    && (child->path.type == DEVICE_PATH_PNP)) {
-				struct resource *res;
-				for (res = child->resource_list; res; res = res->next) {
-					u32 base, end;	/*  don't need long long */
-					u32 rsize, set = 0, set_x = 0;
-					if (!(res->flags & IORESOURCE_IO))
-						continue;
-					base = res->base;
-					end = resource_end(res);
-					/* find a resource size */
-					printk(BIOS_DEBUG, "hudson lpc decode:%s, base=0x%08x, end=0x%08x\n",
-					     dev_path(child), base, end);
-					switch (base) {
-					case 0x60:	/*  KB */
-					case 0x64:	/*  MS */
-						set |= (1 << 29);
-						rsize = 1;
-						break;
-					case 0x3f8:	/*  COM1 */
-						set |= (1 << 6);
-						rsize = 8;
-						break;
-					case 0x2f8:	/*  COM2 */
-						set |= (1 << 7);
-						rsize = 8;
-						break;
-					case 0x378:	/*  Parallel 1 */
-						set |= (1 << 0);
-						set |= (1 << 1); /* + 0x778 for ECP */
-						rsize = 8;
-						break;
-					case 0x3f0:	/*  FD0 */
-						set |= (1 << 26);
-						rsize = 8;
-						break;
-					case 0x220:	/*  0x220 - 0x227 */
-						set |= (1 << 8);
-						rsize = 8;
-						break;
-					case 0x228:	/*  0x228 - 0x22f */
-						set |= (1 << 9);
-						rsize = 8;
-						break;
-					case 0x238:	/*  0x238 - 0x23f */
-						set |= (1 << 10);
-						rsize = 8;
-						break;
-					case 0x300:	/*  0x300 -0x301 */
-						set |= (1 << 18);
-						rsize = 2;
-						break;
-					case 0x400:
-						set_x |= (1 << 16);
-						rsize = 0x40;
-						break;
-					case 0x480:
-						set_x |= (1 << 17);
-						rsize = 0x40;
-						break;
-					case 0x500:
-						set_x |= (1 << 18);
-						rsize = 0x40;
-						break;
-					case 0x580:
-						set_x |= (1 << 19);
-						rsize = 0x40;
-						break;
-					case 0x4700:
-						set_x |= (1 << 22);
-						rsize = 0xc;
-						break;
-					case 0xfd60:
-						set_x |= (1 << 23);
-						rsize = 16;
-						break;
-					default:
-						rsize = 0;
-						/* try AGESA allocated region in region 0 */
-						if ((var_num > 0) && ((base >= reg_var[0]) &&
-								((base + res->size) <= (reg_var[0] + reg_size[0]))))
-							rsize = reg_size[0];
-					}
-					/* check if region found and matches the enable */
-					if (res->size <= rsize) {
-						reg |= set;
-						reg_x |= set_x;
-					/* check if we can fit resource in variable range */
-					} else if ((var_num < 3) &&
-						    ((res->size <= 16) || (res->size == 512))) {
-						/* use variable ranges if pre-defined do not match */
-						switch (var_num) {
-						case 0:
-							reg_x |= (1 << 2);
-							if (res->size <= 16) {
-								wiosize |= (1 << 0);
-							}
-							break;
-						case 1:
-							reg_x |= (1 << 24);
-							if (res->size <= 16)
-								wiosize |= (1 << 2);
-							break;
-						case 2:
-							reg_x |= (1 << 25);
-							if (res->size <= 16)
-								wiosize |= (1 << 3);
-							break;
-						}
-						reg_var[var_num++] =
-						    base & 0xffff;
-					} else {
-						printk(BIOS_ERR, "cannot fit LPC decode region:%s, base=0x%08x, end=0x%08x\n",
-							dev_path(child), base, end);
-					}
-				}
-			}
-		}
-	}
-	pci_write_config32(dev, 0x44, reg);
-	pci_write_config32(dev, 0x48, reg_x);
-	/* Set WideIO for as many IOs found (fall through is on purpose) */
-	switch (var_num) {
-	case 3:
-		pci_write_config16(dev, 0x90, reg_var[2]);
-		__fallthrough;
-	case 2:
-		pci_write_config16(dev, 0x66, reg_var[1]);
-		__fallthrough;
-	case 1:
-		pci_write_config16(dev, 0x64, reg_var[0]);
-		break;
-	}
-	pci_write_config8(dev, 0x74, wiosize);
-}
-
-static void hudson_lpc_enable_resources(struct device *dev)
-{
-	pci_dev_enable_resources(dev);
-	hudson_lpc_enable_childrens_resources(dev);
-}
-
-static const char *lpc_acpi_name(const struct device *dev)
-{
-	if (dev->path.type != DEVICE_PATH_PCI)
-		return NULL;
-
-	if (dev->path.pci.devfn == LPC_DEVFN)
-		return "LIBR";
-
-	return NULL;
-}
-
-static void lpc_final(struct device *dev)
-{
-	if (!acpi_is_wakeup_s3()) {
-		if (CONFIG(HAVE_SMI_HANDLER))
-			outl(0x0, ACPI_PM1_CNT_BLK);	/* clear SCI_EN */
-		else
-			outl(0x1, ACPI_PM1_CNT_BLK);	/* set SCI_EN */
-	}
-}
-
-static struct device_operations lpc_ops = {
-	.read_resources = hudson_lpc_read_resources,
-	.set_resources = hudson_lpc_set_resources,
-	.enable_resources = hudson_lpc_enable_resources,
-#if CONFIG(HAVE_ACPI_TABLES)
-	.write_acpi_tables = acpi_write_hpet,
-#endif
-	.init = lpc_init,
-	.final = lpc_final,
-	.scan_bus = scan_static_bus,
-	.ops_pci = &pci_dev_ops_pci,
-	.acpi_name = lpc_acpi_name,
-};
-static const struct pci_driver lpc_driver __pci_driver = {
-	.ops = &lpc_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_LPC,
-};
diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c
deleted file mode 100644
index b99413c9c4..0000000000
--- a/src/southbridge/amd/agesa/hudson/pci.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "hudson.h"
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <bootstate.h>
-
-/*
- * Update the PCI devices with a valid IRQ number
- * that is set in the mainboard PCI_IRQ structures.
- */
-static void set_pci_irqs(void *unused)
-{
-	/* Write PCI_INTR regs 0xC00/0xC01 */
-	write_pci_int_table();
-
-	/* Write IRQs for all devicetree enabled devices */
-	write_pci_cfg_irqs();
-}
-
-/*
- * Hook this function into the PCI state machine
- * on entry into BS_DEV_ENABLE.
- */
-BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = 0,
-};
-
-static struct device_operations pci_ops = {
-	.read_resources = pci_bus_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.scan_bus = pci_scan_bridge,
-	.reset_bus = pci_bus_reset,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_PCI,
-};
diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h
deleted file mode 100644
index d67395c9ee..0000000000
--- a/src/southbridge/amd/agesa/hudson/pci_devs.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _AGESA_HUDSON_PCI_DEVS_H_
-#define _AGESA_HUDSON_PCI_DEVS_H_
-
-#include <device/pci_def.h>
-
-#define BUS0			0
-
-/* XHCI */
-#define XHCI_DEV		0x10
-#define XHCI_FUNC		0
-#define XHCI_DEVID		0x7814
-#define XHCI_DEVFN		PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
-
-/* SATA */
-#define SATA_DEV		0x11
-#define SATA_FUNC		0
-#define SATA_IDE_DEVID		0x7800
-#define AHCI_DEVID_MS		0x7801
-#define AHCI_DEVID_AMD		0x7804
-#define SATA_DEVFN		PCI_DEVFN(SATA_DEV, SATA_FUNC)
-
-/* OHCI */
-#define OHCI1_DEV		0x12
-#define OHCI1_FUNC		0
-#define OHCI2_DEV		0x13
-#define OHCI2_FUNC		0
-#define OHCI3_DEV		0x16
-#define OHCI3_FUNC		0
-#define OHCI4_DEV		0x14
-#define OHCI4_FUNC		5
-#define OHCI_DEVID		0x7807
-#define OHCI1_DEVFN		PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC)
-#define OHCI2_DEVFN		PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC)
-#define OHCI3_DEVFN		PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC)
-#define OHCI4_DEVFN		PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC)
-
-/* EHCI */
-#define EHCI1_DEV		0x12
-#define EHCI1_FUNC		2
-#define EHCI2_DEV		0x13
-#define EHCI2_FUNC		2
-#define EHCI3_DEV		0x16
-#define EHCI3_FUNC		2
-#define EHCI_DEVID		0x7808
-#define EHCI1_DEVFN		PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC)
-#define EHCI2_DEVFN		PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC)
-#define EHCI3_DEVFN		PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC)
-
-/* SMBUS */
-#define SMBUS_DEV		0x14
-#define SMBUS_FUNC		0
-#define SMBUS_DEVID		0x780B
-#define SMBUS_DEVFN		PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
-
-/* IDE */
-#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
-#define IDE_DEV			0x14
-#define IDE_FUNC		1
-#define IDE_DEVID		0x780C
-#define IDE_DEVFN		PCI_DEVFN(IDE_DEV, IDE_FUNC)
-#endif
-
-/* HD Audio */
-#define HDA_DEV			0x14
-#define HDA_FUNC		2
-#define HDA_DEVID		0x780D
-#define HDA_DEVFN		PCI_DEVFN(HDA_DEV, HDA_FUNC)
-
-/* LPC BUS */
-#define PCU_DEV			0x14
-#define LPC_DEV			PCU_DEV
-#define LPC_FUNC		3
-#define LPC_DEVID		0x780E
-#define LPC_DEVFN		PCI_DEVFN(LPC_DEV, LPC_FUNC)
-
-/* PCI Ports */
-#define SB_PCI_PORT_DEV		0x14
-#define SB_PCI_PORT_FUNC	4
-#define SB_PCI_PORT_DEVID	0x780F
-#define SB_PCI_PORT_DEVFN	PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC)
-
-/* SD Controller */
-#define SD_DEV			0x14
-#define SD_FUNC			7
-#define SD_DEVID		0x7806
-#define SD_DEVFN		PCI_DEVFN(SD_DEV, SD_FUNC)
-
-/* PCIe Ports */
-#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
-#define SB_PCIE_DEV		0x15
-#define SB_PCIE_PORT1_FUNC	0
-#define SB_PCIE_PORT2_FUNC	1
-#define SB_PCIE_PORT3_FUNC	2
-#define SB_PCIE_PORT4_FUNC	3
-#define SB_PCIE_PORT1_DEVID	0x7820
-#define SB_PCIE_PORT2_DEVID	0x7821
-#define SB_PCIE_PORT3_DEVID	0x7822
-#define SB_PCIE_PORT4_DEVID	0x7823
-#define SB_PCIE_PORT1_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC)
-#define SB_PCIE_PORT2_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC)
-#define SB_PCIE_PORT3_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC)
-#define SB_PCIE_PORT4_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC)
-#endif
-
-#endif /* _AGESA_HUDSON_PCI_DEVS_H_ */
diff --git a/src/southbridge/amd/agesa/hudson/pcie.c b/src/southbridge/amd/agesa/hudson/pcie.c
deleted file mode 100644
index 04827a44df..0000000000
--- a/src/southbridge/amd/agesa/hudson/pcie.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "hudson.h"
-
-static void pcie_init(struct device *dev)
-{
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = 0,
-};
-
-static struct device_operations pci_ops = {
-	.read_resources = pci_bus_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init = pcie_init,
-	.scan_bus = pci_scan_bridge,
-	.reset_bus = pci_bus_reset,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver pciea_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_PCIEA,
-};
-
-static const struct pci_driver pcieb_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_PCIEB,
-};
-static const struct pci_driver pciec_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_PCIEC,
-};
-static const struct pci_driver pcied_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_PCIED,
-};
diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c
deleted file mode 100644
index 821fc39bcd..0000000000
--- a/src/southbridge/amd/agesa/hudson/ramtop.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <acpi/acpi.h>
-#include "hudson.h"
-
-int acpi_get_sleep_type(void)
-{
-	u16 tmp = inw(ACPI_PM1_CNT_BLK);
-	tmp = ((tmp & (7 << 10)) >> 10);
-	return (int)tmp;
-}
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
deleted file mode 100644
index fbb62c88fc..0000000000
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
-#include <device/pci_ops.h>
-#include <cf9_reset.h>
-#include <reset.h>
-
-#define HT_INIT_CONTROL		0x6c
-#define HTIC_ColdR_Detect	(1 << 4)
-#define HTIC_BIOSR_Detect	(1 << 5)
-#define HTIC_INIT_Detect	(1 << 6)
-
-void cf9_reset_prepare(void)
-{
-	u32 htic;
-	htic = pci_s_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
-	htic &= ~HTIC_BIOSR_Detect;
-	pci_s_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
-}
-
-void do_board_reset(void)
-{
-	system_reset();
-}
diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c
deleted file mode 100644
index a742e22df9..0000000000
--- a/src/southbridge/amd/agesa/hudson/resume.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <Proc/Fch/FchPlatform.h>
-#include <Proc/Fch/Fch.h>
-#include <device/device.h>
-#include "hudson.h"
-#include <AGESA.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/state_machine.h>
-
-extern FCH_DATA_BLOCK InitEnvCfgDefault;
-extern FCH_INTERFACE FchInterfaceDefault;
-extern FCH_RESET_DATA_BLOCK  InitResetCfgDefault;
-extern FCH_RESET_INTERFACE FchResetInterfaceDefault;
-
-#define DUMP_FCH_SETTING 0
-
-static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
-{
-	*FchParams = InitEnvCfgDefault;
-
-	FchParams->Usb.Xhci0Enable              = InitResetCfgDefault.FchReset.Xhci0Enable;
-	FchParams->Usb.Xhci1Enable              = InitResetCfgDefault.FchReset.Xhci1Enable;
-	FchParams->Spi.SpiFastSpeed             = InitResetCfgDefault.FastSpeed;
-	FchParams->Spi.WriteSpeed               = InitResetCfgDefault.WriteSpeed;
-	FchParams->Spi.SpiMode                  = InitResetCfgDefault.Mode;
-	FchParams->Spi.AutoMode                 = InitResetCfgDefault.AutoMode;
-	FchParams->Spi.SpiBurstWrite            = InitResetCfgDefault.BurstWrite;
-	FchParams->Sata.SataMode.Sata6AhciCap   = (UINT8) InitResetCfgDefault.Sata6AhciCap;
-	FchParams->Misc.Cg2Pll                  = InitResetCfgDefault.Cg2Pll;
-	FchParams->Sata.SataMode.SataSetMaxGen2 = InitResetCfgDefault.SataSetMaxGen2;
-	FchParams->Sata.SataMode.SataClkMode    = InitResetCfgDefault.SataClkMode;
-	FchParams->Sata.SataMode.SataModeReg    = InitResetCfgDefault.SataModeReg;
-	FchParams->Sata.SataInternal100Spread   = (UINT8) InitResetCfgDefault.SataInternal100Spread;
-	FchParams->Spi.SpiSpeed                 = InitResetCfgDefault.SpiSpeed;
-	FchParams->Gpp                          = InitResetCfgDefault.Gpp;
-	FchParams->Gpp.GppFunctionEnable        = FchResetInterfaceDefault.GppEnable;
-
-	FchParams->Gpp.GppLinkConfig           = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
-	FchParams->Gpp.PortCfg[0].PortPresent  = UserOptions.FchBldCfg->CfgFchGppPort0Present;
-	FchParams->Gpp.PortCfg[1].PortPresent  = UserOptions.FchBldCfg->CfgFchGppPort1Present;
-	FchParams->Gpp.PortCfg[2].PortPresent  = UserOptions.FchBldCfg->CfgFchGppPort2Present;
-	FchParams->Gpp.PortCfg[3].PortPresent  = UserOptions.FchBldCfg->CfgFchGppPort3Present;
-	FchParams->Gpp.PortCfg[0].PortHotPlug  = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
-	FchParams->Gpp.PortCfg[1].PortHotPlug  = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
-	FchParams->Gpp.PortCfg[2].PortHotPlug  = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
-	FchParams->Gpp.PortCfg[3].PortHotPlug  = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
-
-	FchParams->HwAcpi.Smbus0BaseAddress    = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
-	FchParams->HwAcpi.Smbus1BaseAddress    = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
-	FchParams->HwAcpi.SioPmeBaseAddress    = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
-	FchParams->HwAcpi.AcpiPm1EvtBlkAddr    = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
-	FchParams->HwAcpi.AcpiPm1CntBlkAddr    = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
-	FchParams->HwAcpi.AcpiPmTmrBlkAddr     = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
-	FchParams->HwAcpi.CpuControlBlkAddr    = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
-	FchParams->HwAcpi.AcpiGpe0BlkAddr      = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
-	FchParams->HwAcpi.SmiCmdPortAddr       = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
-	FchParams->HwAcpi.AcpiPmaCntBlkAddr    = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
-	FchParams->HwAcpi.WatchDogTimerBase    = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
-	FchParams->Sata.SataRaid5Ssid          = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
-	FchParams->Sata.SataRaidSsid           = UserOptions.FchBldCfg->CfgSataRaidSsid;
-	FchParams->Sata.SataAhciSsid           = UserOptions.FchBldCfg->CfgSataAhciSsid;
-	FchParams->Sata.SataIdeSsid            = UserOptions.FchBldCfg->CfgSataIdeSsid;
-	FchParams->Spi.RomBaseAddress          = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
-	FchParams->Sd.SdSsid                   = UserOptions.FchBldCfg->CfgSdSsid;
-	FchParams->Spi.LpcSsid                 = UserOptions.FchBldCfg->CfgLpcSsid;
-	FchParams->Hpet.HpetBase               = UserOptions.FchBldCfg->CfgHpetBaseAddress;
-	FchParams->Azalia.AzaliaSsid           = UserOptions.FchBldCfg->CfgAzaliaSsid;
-	FchParams->Smbus.SmbusSsid             = UserOptions.FchBldCfg->CfgSmbusSsid;
-	FchParams->Ide.IdeSsid                 = UserOptions.FchBldCfg->CfgIdeSsid;
-	FchParams->Usb.EhciSsid                = UserOptions.FchBldCfg->CfgEhciSsid;
-	FchParams->Usb.OhciSsid                = UserOptions.FchBldCfg->CfgOhciSsid;
-	FchParams->Usb.XhciSsid                = UserOptions.FchBldCfg->CfgXhciSsid;
-	FchParams->Ir.IrPinControl             = UserOptions.FchBldCfg->CfgFchIrPinControl;
-	FchParams->Sd.SdClockControl           = UserOptions.FchBldCfg->CfgFchSdClockControl;
-
-	FchParams->Sd.SdConfig                 = FchInterfaceDefault.SdConfig;
-	FchParams->Azalia.AzaliaEnable         = FchInterfaceDefault.AzaliaController;
-	FchParams->Ir.IrConfig                 = FchInterfaceDefault.IrConfig;
-	FchParams->Ab.NbSbGen2                 = FchInterfaceDefault.UmiGen2;
-	FchParams->Sata.SataClass              = FchInterfaceDefault.SataClass;
-	FchParams->Sata.SataMode.SataEnable    = FchInterfaceDefault.SataEnable;
-	FchParams->Sata.SataMode.IdeEnable     = FchInterfaceDefault.IdeEnable;
-	FchParams->Sata.SataIdeMode            = FchInterfaceDefault.SataIdeMode;
-	FchParams->Usb.Ohci1Enable             = FchInterfaceDefault.Ohci1Enable;
-	FchParams->Usb.Ehci1Enable             = FchInterfaceDefault.Ohci1Enable;
-	FchParams->Usb.Ohci2Enable             = FchInterfaceDefault.Ohci2Enable;
-	FchParams->Usb.Ehci2Enable             = FchInterfaceDefault.Ohci2Enable;
-	FchParams->Usb.Ohci3Enable             = FchInterfaceDefault.Ohci3Enable;
-	FchParams->Usb.Ehci3Enable             = FchInterfaceDefault.Ohci3Enable;
-	FchParams->Usb.Ohci4Enable             = FchInterfaceDefault.Ohci4Enable;
-	FchParams->HwAcpi.PwrFailShadow        = FchInterfaceDefault.FchPowerFail;
-
-	FchParams->Usb.Xhci0Enable	= CONFIG(HUDSON_XHCI_ENABLE);
-	FchParams->Usb.Xhci1Enable	= FALSE;
-
-#if DUMP_FCH_SETTING
-	int i;
-
-	for (i = 0; i < sizeof(FchParams); i++) {
-		printk(BIOS_DEBUG, " %02x", ((u8 *)FchParams)[i]);
-		if ((i % 16) == 15)
-			printk(BIOS_DEBUG, "\n");
-	}
-#endif
-}
-
-AGESA_STATUS fchs3earlyrestore(AMD_CONFIG_PARAMS *StdHeader)
-{
-	FCH_DATA_BLOCK      FchParams;
-
-	/* FIXME: Recover FCH_DATA_BLOCK from CBMEM. */
-	s3_resume_init_data(&FchParams);
-
-	FchParams.StdHeader = StdHeader;
-	FchInitS3EarlyRestore(&FchParams);
-	return AGESA_SUCCESS;
-}
-
-AGESA_STATUS fchs3laterestore(AMD_CONFIG_PARAMS *StdHeader)
-{
-	FCH_DATA_BLOCK      FchParams;
-
-	/* FIXME: Recover FCH_DATA_BLOCK from CBMEM. */
-	s3_resume_init_data(&FchParams);
-
-	FchParams.StdHeader = StdHeader;
-	FchInitS3LateRestore(&FchParams);
-
-	return AGESA_SUCCESS;
-}
diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c
deleted file mode 100644
index f04dd5980c..0000000000
--- a/src/southbridge/amd/agesa/hudson/sata.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-
-#include "hudson.h"
-
-static void sata_init(struct device *dev)
-{
-#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-	/**************************************
-	 * Configure the SATA port multiplier *
-	 **************************************/
-	#define BYTE_TO_DWORD_OFFSET(x) (x / 4)
-	#define AHCI_BASE_ADDRESS_REG 0x24
-	#define MISC_CONTROL_REG 0x40
-	#define UNLOCK_BIT (1 << 0)
-	#define SATA_CAPABILITIES_REG 0xFC
-	#define CFG_CAP_SPM (1 << 12)
-
-	volatile u32 *ahci_ptr =
-		(u32*)(uintptr_t)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00);
-	u32 temp;
-
-	/* unlock the write-protect */
-	temp = pci_read_config32(dev, MISC_CONTROL_REG);
-	temp |= UNLOCK_BIT;
-	pci_write_config32(dev, MISC_CONTROL_REG, temp);
-
-	/* set the SATA AHCI mode to allow port expanders */
-	*(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM;
-
-	/* lock the write-protect */
-	temp = pci_read_config32(dev, MISC_CONTROL_REG);
-	temp &= ~UNLOCK_BIT;
-	pci_write_config32(dev, MISC_CONTROL_REG, temp);
-#endif
-};
-
-static struct pci_operations lops_pci = {
-	/* .set_subsystem = pci_dev_set_subsystem, */
-};
-
-static struct device_operations sata_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = sata_init,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver sata0_driver __pci_driver = {
-	.ops = &sata_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_SATA,
-};
-
-static const struct pci_driver sata0_driver_ahci __pci_driver = {
-	.ops = &sata_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_SATA_AHCI,
-};
diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c
deleted file mode 100644
index f3ea0a5eb4..0000000000
--- a/src/southbridge/amd/agesa/hudson/sd.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-
-#include "chip.h"
-#include "hudson.h"
-
-static void sd_init(struct device *dev)
-{
-	struct southbridge_amd_agesa_hudson_config *sd_chip = dev->chip_info;
-	u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC);
-	u8 sd_mode = 0;
-
-	if (sd_chip)
-		sd_mode = sd_chip->sd_mode;
-
-	if (sd_mode == 3) {	/* SD 3.0 mode */
-		pci_write_config32(dev, 0xA4, 0x31FEC8B2);
-		pci_write_config32(dev, 0xA8, 0x00002503);
-		pci_write_config32(dev, 0xB0, 0x02180C19);
-		pci_write_config32(dev, 0xD0, 0x0000078B);
-	}
-	else {				/* SD 2.0 mode */
-		if ((stepping & 0x0000000F) == 0) {	/* Stepping A0 */
-			pci_write_config32(dev, 0xA4, 0x31DE32B2);
-			pci_write_config32(dev, 0xB0, 0x01180C19);
-			pci_write_config32(dev, 0xD0, 0x0000058B);
-		}
-		else {					/* Stepping >= A1 */
-			pci_write_config32(dev, 0xA4, 0x31FE3FB2);
-			pci_write_config32(dev, 0xB0, 0x01180C19);
-			pci_write_config32(dev, 0xD0, 0x0000078B);
-		}
-	}
-}
-
-static struct device_operations sd_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = sd_init,
-};
-
-static const struct pci_driver sd_driver __pci_driver = {
-	.ops = &sd_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_YANGTZE_SD,
-};
diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c
deleted file mode 100644
index 8fd124a5a3..0000000000
--- a/src/southbridge/amd/agesa/hudson/sm.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/smbus.h>
-#include <arch/ioapic.h>
-
-#include "hudson.h"
-#include "smbus.c"
-
-#define NMI_OFF 0
-
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON 1
-
-/*
-* HUDSON enables all USB controllers by default in SMBUS Control.
-* HUDSON enables SATA by default in SMBUS Control.
-*/
-
-static void sm_init(struct device *dev)
-{
-	setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
-}
-
-static int lsmbus_recv_byte(struct device *dev)
-{
-	u32 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_recv_byte(res->base, device);
-}
-
-static int lsmbus_send_byte(struct device *dev, u8 val)
-{
-	u32 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_send_byte(res->base, device, val);
-}
-
-static int lsmbus_read_byte(struct device *dev, u8 address)
-{
-	u32 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_read_byte(res->base, device, address);
-}
-
-static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
-{
-	u32 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_write_byte(res->base, device, address, val);
-}
-static struct smbus_bus_operations lops_smbus_bus = {
-	.recv_byte = lsmbus_recv_byte,
-	.send_byte = lsmbus_send_byte,
-	.read_byte = lsmbus_read_byte,
-	.write_byte = lsmbus_write_byte,
-};
-
-static void hudson_sm_read_resources(struct device *dev)
-{
-}
-
-static void hudson_sm_set_resources(struct device *dev)
-{
-}
-
-static struct device_operations smbus_ops = {
-	.read_resources = hudson_sm_read_resources,
-	.set_resources = hudson_sm_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = sm_init,
-	.scan_bus = scan_smbus,
-	.ops_pci = &pci_dev_ops_pci,
-	.ops_smbus_bus = &lops_smbus_bus,
-};
-static const struct pci_driver smbus_driver __pci_driver = {
-	.ops = &smbus_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_SM,
-};
diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c
deleted file mode 100644
index 43f8ca75d3..0000000000
--- a/src/southbridge/amd/agesa/hudson/smbus.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _HUDSON_SMBUS_C_
-#define _HUDSON_SMBUS_C_
-
-#include <arch/io.h>
-#include <stdint.h>
-#include "smbus.h"
-
-static int smbus_wait_until_ready(u32 smbus_io_base)
-{
-	u32 loops;
-
-	loops = SMBUS_TIMEOUT;
-	do {
-		u8 val;
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f;
-		if (val == 0) {	/* ready now */
-			return 0;
-		}
-		outb(val, smbus_io_base + SMBHSTSTAT);
-	} while (--loops);
-
-	return -2;		/* time out */
-}
-
-static int smbus_wait_until_done(u32 smbus_io_base)
-{
-	u32 loops;
-
-	loops = SMBUS_TIMEOUT;
-	do {
-		u8 val;
-
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f;	/* mask off reserved bits */
-		if (val & 0x1c) {
-			return -5;	/* error */
-		}
-		if (val == 0x02) {
-			outb(val, smbus_io_base + SMBHSTSTAT);	/* clear status */
-			return 0;
-		}
-	} while (--loops);
-
-	return -3;		/* timeout */
-}
-
-int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2;	/* not ready */
-	}
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTCMD);
-
-	return byte;
-}
-
-int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2;	/* not ready */
-	}
-
-	/* set the command... */
-	outb(val, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	return 0;
-}
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2;	/* not ready */
-	}
-
-	/* set the command/address... */
-	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTDAT0);
-
-	return byte;
-}
-
-int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2;	/* not ready */
-	}
-
-	/* set the command/address... */
-	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
-
-	/* output value */
-	outb(val, smbus_io_base + SMBHSTDAT0);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	return 0;
-}
-
-void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
-{
-	u32 tmp;
-
-	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
-	tmp = inl(AB_DATA);
-	/* rpr 4.2
-	 * For certain revisions of the chip, the ABCFG registers,
-	 * with an address of 0x100NN (where 'N' is any hexadecimal
-	 * number), require an extra programming step.*/
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
-	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-}
-
-void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
-{
-	u32 tmp;
-
-	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
-	tmp = inl(AB_DATA);
-	/* rpr 4.2
-	 * For certain revisions of the chip, the ABCFG registers,
-	 * with an address of 0x100NN (where 'N' is any hexadecimal
-	 * number), require an extra programming step.*/
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
-	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-}
-
-/* space = 0: AX_INDXC, AX_DATAC
- * space = 1: AX_INDXP, AX_DATAP
- */
-void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val)
-{
-	u32 tmp;
-
-	/* read axindc to tmp */
-	outl(space << 29 | space << 3 | 0x30, AB_INDX);
-	outl(axindc, AB_DATA);
-	outl(0, AB_INDX);
-	outl(space << 29 | space << 3 | 0x34, AB_INDX);
-	tmp = inl(AB_DATA);
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	/* write tmp */
-	outl(space << 29 | space << 3 | 0x30, AB_INDX);
-	outl(axindc, AB_DATA);
-	outl(0, AB_INDX);
-	outl(space << 29 | space << 3 | 0x34, AB_INDX);
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-}
-#endif
diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h
deleted file mode 100644
index ecee071462..0000000000
--- a/src/southbridge/amd/agesa/hudson/smbus.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef HUDSON_SMBUS_H
-#define HUDSON_SMBUS_H
-
-#include <stdint.h>
-
-#define SMBHSTSTAT		0x0
-#define SMBSLVSTAT		0x1
-#define SMBHSTCTRL		0x2
-#define SMBHSTCMD		0x3
-#define SMBHSTADDR		0x4
-#define SMBHSTDAT0		0x5
-#define SMBHSTDAT1		0x6
-#define SMBHSTBLKDAT		0x7
-
-#define SMBSLVCTRL		0x8
-#define SMBSLVCMD_SHADOW	0x9
-#define SMBSLVEVT		0xa
-#define SMBSLVDAT		0xc
-
-#define AX_INDXC		0
-#define AX_INDXP		2
-#define AXCFG			4
-#define ABCFG			6
-#define RC_INDXC		1
-#define RC_INDXP		3
-
-#define AB_INDX			0xcd8
-#define AB_DATA			(AB_INDX + 4)
-
-/* Between 1-10 seconds, We should never timeout normally
- * Longer than this is just painful when a timeout condition occurs.
- */
-#define SMBUS_TIMEOUT (100 * 1000 * 10)
-
-#define abcfg_reg(reg, mask, val)	\
-	alink_ab_indx((ABCFG), (reg), (mask), (val))
-#define axcfg_reg(reg, mask, val)	\
-	alink_ab_indx((AXCFG), (reg), (mask), (val))
-#define axindxc_reg(reg, mask, val)	\
-	alink_ax_indx((AX_INDXC), (reg), (mask), (val))
-#define axindxp_reg(reg, mask, val)		\
-	alink_ax_indx((AX_INDXP), (reg), (mask), (val))
-#define rcindxc_reg(reg, port, mask, val)	\
-	alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
-#define rcindxp_reg(reg, port, mask, val)	\
-	alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
-int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
-int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
-void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
-void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
-void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val);
-
-#endif
diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c
deleted file mode 100644
index c240e5b877..0000000000
--- a/src/southbridge/amd/agesa/hudson/smbus_spd.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/pci_def.h>
-#include <device/device.h>
-#include <console/console.h>
-#include <stddef.h>
-/* warning: Porting.h includes an open #pragma pack(1) */
-#include <Porting.h>
-#include <AGESA.h>
-#include <amdlib.h>
-#include <northbridge/amd/agesa/dimmSpd.h>
-
-/*-----------------------------------------------------------------------------
- *
- * readSmbusByteData - read a single SPD byte from any offset
- */
-
-static int readSmbusByteData(int iobase, int address, char *buffer, int offset)
-{
-	unsigned int status;
-	UINT64 limit;
-
-	address |= 1; // set read bit
-
-	__outbyte(iobase + 0, 0xFF);                // clear error status
-	__outbyte(iobase + 1, 0x1F);                // clear error status
-	__outbyte(iobase + 3, offset);              // offset in eeprom
-	__outbyte(iobase + 4, address);             // slave address and read bit
-	__outbyte(iobase + 2, 0x48);                // read byte command
-
-	// time limit to avoid hanging for unexpected error status (should never happen)
-	limit = __rdtsc() + 2000000000 / 10;
-	for (;;)
-	{
-		status = __inbyte(iobase);
-		if (__rdtsc() > limit) break;
-		if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
-		if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
-		break;
-	}
-
-	buffer [0] = __inbyte(iobase + 5);
-	if (status == 2) status = 0;                      // check for done with no errors
-	return status;
-}
-
-/*-----------------------------------------------------------------------------
- *
- * readSmbusByte - read a single SPD byte from the default offset
- *                 this function is faster function readSmbusByteData
- */
-
-static int readSmbusByte(int iobase, int address, char *buffer)
-{
-	unsigned int status;
-	UINT64 limit;
-
-	__outbyte(iobase + 0, 0xFF);                // clear error status
-	__outbyte(iobase + 2, 0x44);                // read command
-
-	// time limit to avoid hanging for unexpected error status
-	limit = __rdtsc() + 2000000000 / 10;
-	for (;;)
-	{
-		status = __inbyte(iobase);
-		if (__rdtsc() > limit) break;
-		if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
-		if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
-		break;
-	}
-
-	buffer [0] = __inbyte(iobase + 5);
-	if (status == 2) status = 0;                      // check for done with no errors
-	return status;
-}
-
-/*---------------------------------------------------------------------------
- *
- * readspd - Read one or more SPD bytes from a DIMM.
- *           Start with offset zero and read sequentially.
- *           Optimization relies on autoincrement to avoid
- *           sending offset for every byte.
- *          Reads 128 bytes in 7-8 ms at 400 KHz.
- */
-
-static int readspd(int iobase, int SmbusSlaveAddress, char *buffer, int count)
-{
-	int index, error;
-
-	printk(BIOS_SPEW, "-------------READING SPD-----------\n");
-	printk(BIOS_SPEW, "iobase: 0x%08X, SmbusSlave: 0x%08X, count: %d\n",
-						iobase, SmbusSlaveAddress, count);
-
-	/* read the first byte using offset zero */
-	error = readSmbusByteData(iobase, SmbusSlaveAddress, buffer, 0);
-
-	if (error) {
-		printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
-		return error;
-	}
-
-	/* read the remaining bytes using auto-increment for speed */
-	for (index = 1; index < count; index++)
-	{
-		error = readSmbusByte(iobase, SmbusSlaveAddress, &buffer [index]);
-		if (error) {
-			printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
-			return error;
-		}
-	}
-	printk(BIOS_SPEW, "\n");
-	printk(BIOS_SPEW, "-------------FINISHED READING SPD-----------\n");
-
-	return 0;
-}
-
-static void setupFch(int ioBase)
-{
-	pm_write16(0x2c, ioBase | 1);
-	__outbyte(ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
-}
-
-int hudson_readSpd(int spdAddress, char *buf, size_t len)
-{
-	int ioBase = 0xB00;
-	setupFch(ioBase);
-	return readspd(ioBase, spdAddress, buf, len);
-}
diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c
deleted file mode 100644
index 560b66679b..0000000000
--- a/src/southbridge/amd/agesa/hudson/smi.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * Utilities for SMM setup
- */
-
-#include <amdblocks/acpimmio.h>
-#include <cpu/x86/smm.h>
-
-#include "smi.h"
-
-/** Set the EOS bit and enable SMI generation from southbridge */
-void global_smi_enable(void)
-{
-	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
-	reg &= ~SMITRG0_SMIENB;	/* Enable SMI generation */
-	reg |= SMITRG0_EOS;	/* Set EOS bit */
-	smi_write32(SMI_REG_SMITRIG0, reg);
-}
diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h
deleted file mode 100644
index d0187b8c16..0000000000
--- a/src/southbridge/amd/agesa/hudson/smi.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * Utilities for SMI handlers and SMM setup
- */
-
-#ifndef _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H
-#define _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H
-
-#include <device/mmio.h>
-
-/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it.
- * This is defined by AGESA, but we dpn't include AGESA headers to avoid
- * polluting the namesace.
- */
-#define SMI_BASE 0xfed80200
-
-#define SMI_REG_SMITRIG0	0x98
-#define SMITRG0_EOS		(1 << 28)
-#define SMITRG0_SMIENB		(1 << 31)
-
-#define SMI_REG_CONTROL0	0xa0
-
-enum smi_mode {
-	SMI_MODE_DISABLE = 0,
-	SMI_MODE_SMI = 1,
-	SMI_MODE_NMI = 2,
-	SMI_MODE_IRQ13 = 3,
-};
-
-enum smi_lvl {
-	SMI_LVL_LOW = 0,
-	SMI_LVL_HIGH = 1,
-};
-
-void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
-void hudson_disable_gevent_smi(uint8_t gevent);
-void hudson_enable_acpi_cmd_smi(void);
-
-#endif /* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */
diff --git a/src/southbridge/amd/agesa/hudson/smi_util.c b/src/southbridge/amd/agesa/hudson/smi_util.c
deleted file mode 100644
index 3dc2d8a31e..0000000000
--- a/src/southbridge/amd/agesa/hudson/smi_util.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * SMM utilities used in both SMM and normal mode
- */
-
-#include <amdblocks/acpimmio.h>
-#include <console/console.h>
-
-#include "smi.h"
-
-#define HUDSON_SMI_ACPI_COMMAND		75
-
-static void configure_smi(uint8_t smi_num, uint8_t mode)
-{
-	uint8_t reg32_offset, bit_offset;
-	uint32_t reg32;
-
-	/* SMI sources range from [0:149] */
-	if (smi_num > 149) {
-		printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num);
-		return;
-	}
-
-	/* 16 sources per register, 2 bits per source; registers are 4 bytes */
-	reg32_offset = (smi_num / 16) * 4;
-	bit_offset = (smi_num % 16) * 2;
-
-	reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset);
-	reg32 &= ~(0x3 << (bit_offset));
-	reg32 |= (mode & 0x3) << bit_offset;
-	smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32);
-}
-
-/**
- * Configure generation of interrupts for given GEVENT pin
- *
- * @param gevent The GEVENT pin number. Valid values are 0 thru 23
- * @param mode The type of event this pin should generate. Note that only
- *	       SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events.
- * @param level SMI_LVL_LOW or SMI_LVL_HIGH
- */
-void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level)
-{
-	uint32_t reg32;
-	/* GEVENT pins range from [0:23] */
-	if (gevent > 23) {
-		printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent);
-		return;
-	}
-
-	/* SMI0 source is GEVENT0 and so on */
-	configure_smi(gevent, mode);
-
-	/* And set the trigger level */
-	reg32 = smi_read32(SMI_REG_SMITRIG0);
-	reg32 &= ~(1 << gevent);
-	reg32 |= (level & 0x1) << gevent;
-	smi_write32(SMI_REG_SMITRIG0, reg32);
-}
-
-/** Disable events from given GEVENT pin */
-void hudson_disable_gevent_smi(uint8_t gevent)
-{
-	/* GEVENT pins range from [0:23] */
-	if (gevent > 23) {
-		printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent);
-		return;
-	}
-
-	/* SMI0 source is GEVENT0 and so on */
-	configure_smi(gevent, SMI_MODE_DISABLE);
-}
-
-/** Enable SMIs on writes to ACPI SMI command port */
-void hudson_enable_acpi_cmd_smi(void)
-{
-	configure_smi(HUDSON_SMI_ACPI_COMMAND, SMI_MODE_SMI);
-}
diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c
deleted file mode 100644
index a942c24ada..0000000000
--- a/src/southbridge/amd/agesa/hudson/smihandler.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * SMI handler for Hudson southbridges
- */
-
-#include <amdblocks/acpimmio.h>
-#include <arch/io.h>
-#include <cpu/x86/smm.h>
-
-#include "hudson.h"
-#include "smi.h"
-
-#define SMI_0x88_ACPI_COMMAND		(1 << 11)
-
-enum smi_source {
-	SMI_SOURCE_SCI = (1 << 0),
-	SMI_SOURCE_GPE = (1 << 1),
-	SMI_SOURCE_0x84 = (1 << 2),
-	SMI_SOURCE_0x88 = (1 << 3),
-	SMI_SOURCE_IRQ_TRAP = (1 << 4),
-	SMI_SOURCE_0x90 = (1 << 5)
-};
-
-static void hudson_apmc_smi_handler(void)
-{
-	u32 reg32;
-	const uint8_t cmd = inb(ACPI_SMI_CTL_PORT);
-
-	switch (cmd) {
-	case ACPI_SMI_CMD_ENABLE:
-		reg32 = inl(ACPI_PM1_CNT_BLK);
-		reg32 |= (1 << 0);	/* SCI_EN */
-		outl(reg32, ACPI_PM1_CNT_BLK);
-		break;
-	case ACPI_SMI_CMD_DISABLE:
-		reg32 = inl(ACPI_PM1_CNT_BLK);
-		reg32 &= ~(1 << 0);	/* clear SCI_EN */
-		outl(ACPI_PM1_CNT_BLK, reg32);
-		break;
-	}
-
-	mainboard_smi_apmc(cmd);
-}
-
-int southbridge_io_trap_handler(int smif)
-{
-	return 0;
-}
-
-static void process_smi_sci(void)
-{
-	const uint32_t status = smi_read32(0x10);
-
-	/* Clear events to prevent re-entering SMI if event isn't handled */
-	smi_write32(0x10, status);
-}
-
-static void process_gpe_smi(void)
-{
-	const uint32_t status = smi_read32(0x80);
-	const uint32_t gevent_mask = (1 << 24) - 1;
-
-	/* Only Bits [23:0] indicate GEVENT SMIs. */
-	if (status & gevent_mask) {
-		/* A GEVENT SMI occurred */
-		mainboard_smi_gpi(status & gevent_mask);
-	}
-
-	/* Clear events to prevent re-entering SMI if event isn't handled */
-	smi_write32(0x80, status);
-}
-
-static void process_smi_0x84(void)
-{
-	const uint32_t status = smi_read32(0x84);
-
-	/* Clear events to prevent re-entering SMI if event isn't handled */
-	smi_write32(0x84, status);
-}
-
-static void process_smi_0x88(void)
-{
-	const uint32_t status = smi_read32(0x88);
-
-	if (status & SMI_0x88_ACPI_COMMAND) {
-		/* Command received via ACPI SMI command port */
-		hudson_apmc_smi_handler();
-	}
-	/* Clear events to prevent re-entering SMI if event isn't handled */
-	smi_write32(0x88, status);
-}
-
-static void process_smi_0x8c(void)
-{
-	const uint32_t status = smi_read32(0x8c);
-
-	/* Clear events to prevent re-entering SMI if event isn't handled */
-	smi_write32(0x8c, status);
-}
-
-static void process_smi_0x90(void)
-{
-	const uint32_t status = smi_read32(0x90);
-
-	/* Clear events to prevent re-entering SMI if event isn't handled */
-	smi_write32(0x90, status);
-}
-
-void southbridge_smi_handler(void)
-{
-	const uint16_t smi_src = smi_read16(0x94);
-
-	if (smi_src & SMI_SOURCE_SCI)
-		process_smi_sci();
-	if (smi_src & SMI_SOURCE_GPE)
-		process_gpe_smi();
-	if (smi_src & SMI_SOURCE_0x84)
-		process_smi_0x84();
-	if (smi_src & SMI_SOURCE_0x88)
-		process_smi_0x88();
-	if (smi_src & SMI_SOURCE_IRQ_TRAP)
-		process_smi_0x8c();
-	if (smi_src & SMI_SOURCE_0x90)
-		process_smi_0x90();
-}
-
-void southbridge_smi_set_eos(void)
-{
-	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
-	reg |= SMITRG0_EOS;
-	smi_write32(SMI_REG_SMITRIG0, reg);
-}
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
deleted file mode 100644
index 986f094a77..0000000000
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <stdint.h>
-#include <device/mmio.h>
-#include <console/console.h>
-#include <spi_flash.h>
-#include <spi-generic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <stddef.h>
-
-#include <Proc/Fch/FchPlatform.h>
-
-#define SPI_REG_OPCODE		0x0
-#define SPI_REG_CNTRL01		0x1
-#define SPI_REG_CNTRL02		0x2
- #define CNTRL02_FIFO_RESET	(1 << 4)
- #define CNTRL02_EXEC_OPCODE	(1 << 0)
-#define SPI_REG_CNTRL03		0x3
- #define CNTRL03_SPIBUSY	(1 << 7)
-#define SPI_REG_FIFO		0xc
-#define SPI_REG_CNTRL11		0xd
- #define CNTRL11_FIFOPTR_MASK	0x07
-
-#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-#define AMD_SB_SPI_TX_LEN	64
-#else
-#define AMD_SB_SPI_TX_LEN	8
-#endif
-
-static uintptr_t spibar;
-
-static inline uint8_t spi_read(uint8_t reg)
-{
-	return read8((void *)(spibar + reg));
-}
-
-static inline void spi_write(uint8_t reg, uint8_t val)
-{
-	write8((void *)(spibar + reg), val);
-}
-
-static void reset_internal_fifo_pointer(void)
-{
-	uint8_t reg8;
-
-	do {
-		reg8 = spi_read(SPI_REG_CNTRL02);
-		reg8 |= CNTRL02_FIFO_RESET;
-		spi_write(SPI_REG_CNTRL02, reg8);
-	} while (spi_read(SPI_REG_CNTRL11) & CNTRL11_FIFOPTR_MASK);
-}
-
-static void execute_command(void)
-{
-	uint8_t reg8;
-
-	reg8 = spi_read(SPI_REG_CNTRL02);
-	reg8 |= CNTRL02_EXEC_OPCODE;
-	spi_write(SPI_REG_CNTRL02, reg8);
-
-	while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) &&
-	       (spi_read(SPI_REG_CNTRL03) & CNTRL03_SPIBUSY));
-}
-
-void spi_init(void)
-{
-	struct device *dev;
-
-	dev = pcidev_on_root(0x14, 3);
-	spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
-}
-
-static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
-		size_t bytesout, void *din, size_t bytesin)
-{
-	/* First byte is cmd which can not be sent through FIFO. */
-	u8 cmd = *(u8 *)dout++;
-	u8 readoffby1;
-	size_t count;
-
-	bytesout--;
-
-	/*
-	 * Check if this is a write command attempting to transfer more bytes
-	 * than the controller can handle. Iterations for writes are not
-	 * supported here because each SPI write command needs to be preceded
-	 * and followed by other SPI commands, and this sequence is controlled
-	 * by the SPI chip driver.
-	 */
-	if (bytesout > AMD_SB_SPI_TX_LEN) {
-		printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use"
-		     " spi_crop_chunk()?\n");
-		return -1;
-	}
-
-	readoffby1 = bytesout ? 0 : 1;
-
-	if (CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)) {
-		spi_write(0x1E, 5);
-		spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */
-		spi_write(0x1E, 6);
-		spi_write(0x1F, bytesin);  /* SpiExtRegIndx [6] - RxByteCount */
-	} else {
-		u8 readwrite = (bytesin + readoffby1) << 4 | bytesout;
-		spi_write(SPI_REG_CNTRL01, readwrite);
-	}
-	spi_write(SPI_REG_OPCODE, cmd);
-
-	reset_internal_fifo_pointer();
-	for (count = 0; count < bytesout; count++, dout++) {
-		spi_write(SPI_REG_FIFO, *(uint8_t *)dout);
-	}
-
-	reset_internal_fifo_pointer();
-	execute_command();
-
-	reset_internal_fifo_pointer();
-	/* Skip the bytes we sent. */
-	for (count = 0; count < bytesout; count++) {
-		spi_read(SPI_REG_FIFO);
-	}
-
-	for (count = 0; count < bytesin; count++, din++) {
-		*(uint8_t *)din = spi_read(SPI_REG_FIFO);
-	}
-
-	return 0;
-}
-
-int chipset_volatile_group_begin(const struct spi_flash *flash)
-{
-	if (!CONFIG(HUDSON_IMC_FWM))
-		return 0;
-
-	ImcSleep(NULL);
-	return 0;
-}
-
-int chipset_volatile_group_end(const struct spi_flash *flash)
-{
-	if (!CONFIG(HUDSON_IMC_FWM))
-		return 0;
-
-	ImcWakeup(NULL);
-	return 0;
-}
-
-static int xfer_vectors(const struct spi_slave *slave,
-			struct spi_op vectors[], size_t count)
-{
-	return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);
-}
-
-static const struct spi_ctrlr spi_ctrlr = {
-	.xfer_vector = xfer_vectors,
-	.max_xfer_size = AMD_SB_SPI_TX_LEN,
-	.flags = SPI_CNTRLR_DEDUCT_CMD_LEN,
-};
-
-const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
-	{
-		.ctrlr = &spi_ctrlr,
-		.bus_start = 0,
-		.bus_end = 0,
-	},
-};
-
-const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
diff --git a/src/southbridge/amd/agesa/hudson/usb.c b/src/southbridge/amd/agesa/hudson/usb.c
deleted file mode 100644
index 694f2bfd77..0000000000
--- a/src/southbridge/amd/agesa/hudson/usb.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ehci.h>
-#include "hudson.h"
-
-static void usb_init(struct device *dev)
-{
-}
-
-static struct device_operations usb_ops = {
-	.read_resources = pci_ehci_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = usb_init,
-	.ops_pci = &pci_dev_ops_pci,
-};
-
-static const struct pci_driver usb_0_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_USB_18_0,
-};
-
-static const struct pci_driver usb_1_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_USB_18_2,
-};
-
-static const struct pci_driver usb_4_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VID_AMD,
-	.device = PCI_DID_AMD_SB900_USB_20_5,
-};
diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig
deleted file mode 100644
index 59444f171f..0000000000
--- a/src/southbridge/amd/cimx/Kconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config AMD_SB_CIMX
-	bool
-	default n
-
-source "src/southbridge/amd/cimx/sb800/Kconfig"
diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc
deleted file mode 100644
index f814729753..0000000000
--- a/src/southbridge/amd/cimx/Makefile.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h
deleted file mode 100644
index c6ba09f282..0000000000
--- a/src/southbridge/amd/cimx/sb800/Amd.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/*****************************************************************************
- * AMD Generic Encapsulated Software Architecture                            */
-/**
- * @file
- *
- * Agesa structures and definitions
- *
- * Contains AMD AGESA/CIMx core interface
- *
- */
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _AMD_H_
-#define _AMD_H_
-
-// AGESA Types and Definitions
-#ifndef NULL
-  #define NULL 0
-#endif
-
-#define LAST_ENTRY 0xFFFFFFFF
-#define IOCF8 0xCF8
-#define IOCFC 0xCFC
-#define IN
-#define OUT
-
-#ifndef Int16FromChar
-#define Int16FromChar(a, b) ((a) << 0 | (b) << 8)
-#endif
-#ifndef Int32FromChar
-#define Int32FromChar(a, b, c, d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
-#endif
-
-#define IMAGE_SIGNATURE     Int32FromChar('$', 'A', 'M', 'D')
-
-typedef unsigned int AGESA_STATUS;
-
-#define AGESA_SUCCESS       ((AGESA_STATUS) 0x0)
-#define AGESA_ALERT         ((AGESA_STATUS) 0x40000000)
-#define AGESA_WARNING       ((AGESA_STATUS) 0x40000001)
-#define AGESA_UNSUPPORTED   ((AGESA_STATUS) 0x80000003)
-#define AGESA_ERROR         ((AGESA_STATUS) 0xC0000001)
-#define AGESA_CRITICAL      ((AGESA_STATUS) 0xC0000002)
-#define AGESA_FATAL         ((AGESA_STATUS) 0xC0000003)
-
-typedef AGESA_STATUS(*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2,
-				       void *ConfigPtr);
-typedef AGESA_STATUS(*IMAGE_ENTRY) (IN OUT void *ConfigPtr);
-typedef AGESA_STATUS(*MODULE_ENTRY) (IN OUT void *ConfigPtr);
-
-///This allocation type is used by the AmdCreateStruct entry point
-typedef enum {
-  PreMemHeap = 0,                                           ///< Create heap in cache.
-  PostMemDram,                                              ///< Create heap in memory.
-  ByHost                                                    ///< Create heap by Host.
-} ALLOCATION_METHOD;
-
-/// These width descriptors are used by the library function, and others, to specify the data size
-typedef enum ACCESS_WIDTH {
-  AccessWidth8 = 1,                                         ///< Access width is 8 bits.
-  AccessWidth16,                                            ///< Access width is 16 bits.
-  AccessWidth32,                                            ///< Access width is 32 bits.
-  AccessWidth64,                                            ///< Access width is 64 bits.
-
-  AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
-  AccessS3SaveWidth16,                                      ///< Save 16 bits data.
-  AccessS3SaveWidth32,                                      ///< Save 32 bits data.
-  AccessS3SaveWidth64,                                      ///< Save 64 bits data.
-} ACCESS_WIDTH;
-
-// AGESA Structures
-
-/// The standard header for all AGESA services.
-typedef struct _AMD_CONFIG_PARAMS {
-  IN       unsigned int          ImageBasePtr;     ///< The AGESA Image base address.
-  IN       unsigned int          Func;             ///< The service desired, @sa dispatch.h.
-  IN       unsigned int          AltImageBasePtr;  ///< Alternate Image location
-  IN       unsigned int          PcieBasePtr;      ///< PCIe MMIO Base address, if configured.
-  union {                                    ///< Callback pointer
-    IN       unsigned long long          PlaceHolder;    ///< Place holder
-    IN       CALLOUT_ENTRY   CalloutPtr;     ///< For Callout from AGESA
-  } CALLBACK;
-  IN OUT   unsigned int          Reserved[2];      ///< This space is reserved for future use.
-} AMD_CONFIG_PARAMS;
-
-/// AGESA Binary module header structure
-typedef struct _AMD_IMAGE_HEADER {
-  IN       unsigned int  Signature;                          ///< Binary Signature
-  IN       signed char   CreatorID[8];                       ///< 8 characters ID
-  IN       signed char   Version[12];                        ///< 12 characters version
-  IN       unsigned int  ModuleInfoOffset;                   ///< Offset of module
-  IN       unsigned int  EntryPointAddress;                  ///< Entry address
-  IN       unsigned int  ImageBase;                          ///< Image base
-  IN       unsigned int  RelocTableOffset;                   ///< Relocate Table offset
-  IN       unsigned int  ImageSize;                          ///< Size
-  IN       unsigned short  Checksum;                           ///< Checksum
-  IN       unsigned char   ImageType;                          ///< Type
-  IN       unsigned char   V_Reserved;                         ///< Reserved
-} AMD_IMAGE_HEADER;
-
-/// AGESA Binary module header structure
-typedef struct _AMD_MODULE_HEADER {
-  IN       unsigned int          ModuleHeaderSignature;      ///< Module signature
-  IN       signed char           ModuleIdentifier[8];        ///< 8 characters ID
-  IN       signed char           ModuleVersion[12];          ///< 12 characters version
-  IN       MODULE_ENTRY    ModuleDispatcherPtr;        ///< A pointer point to dispatcher
-  IN       struct _AMD_MODULE_HEADER  *NextBlockPtr;    ///< Next module header link
-} AMD_MODULE_HEADER;
-
-#define FUNC_0    0   // bit-placed for PCI address creation
-#define FUNC_1    1
-#define FUNC_2    2
-#define FUNC_3    3
-#define FUNC_4    4
-#define FUNC_5    5
-#define FUNC_6    6
-#define FUNC_7    7
-
-//   SBDFO - Segment Bus Device Function Offset
-//   31:28   Segment (4-bits)
-//   27:20   Bus     (8-bits)
-//   19:15   Device  (5-bits)
-//   14:12   Function (3-bits)
-//   11:00   Offset  (12-bits)
-
-#define ILLEGAL_SBDFO 0xFFFFFFFF
-
-/// CPUID data received registers format
-typedef struct _CPUID_DATA {
-  IN OUT   unsigned int          EAX_Reg;                ///< CPUID instruction result in EAX
-  IN OUT   unsigned int          EBX_Reg;                ///< CPUID instruction result in EBX
-  IN OUT   unsigned int          ECX_Reg;                ///< CPUID instruction result in ECX
-  IN OUT   unsigned int          EDX_Reg;                ///< CPUID instruction result in EDX
-} CPUID_DATA;
-
-#define WARM_RESET 1
-#define COLD_RESET 2      // Cold reset
-#define RESET_CPU  4      // Triggers a CPU reset
-
-/// HT frequency for external callbacks
-typedef enum {
-  HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
-  HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
-  HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
-  HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
-  HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
-  HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
-  HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
-  HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
-  HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
-  HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
-  HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
-  HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
-  HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
-  HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
-  HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
-  HT_FREQUENCY_3200M         = 19                 ///< HT speed 3200 for external callbacks
-} HT_FREQUENCIES;
-
-#ifndef BIT0
-  #define BIT0        0x0000000000000001ull
-#endif
-#ifndef BIT1
-  #define BIT1        0x0000000000000002ull
-#endif
-#ifndef BIT2
-  #define BIT2        0x0000000000000004ull
-#endif
-#ifndef BIT3
-  #define BIT3        0x0000000000000008ull
-#endif
-#ifndef BIT4
-  #define BIT4        0x0000000000000010ull
-#endif
-#ifndef BIT5
-  #define BIT5        0x0000000000000020ull
-#endif
-#ifndef BIT6
-  #define BIT6        0x0000000000000040ull
-#endif
-#ifndef BIT7
-  #define BIT7        0x0000000000000080ull
-#endif
-#ifndef BIT8
-  #define BIT8        0x0000000000000100ull
-#endif
-#ifndef BIT9
-  #define BIT9        0x0000000000000200ull
-#endif
-#ifndef BIT10
-  #define BIT10       0x0000000000000400ull
-#endif
-#ifndef BIT11
-  #define BIT11       0x0000000000000800ull
-#endif
-#ifndef BIT12
-  #define BIT12       0x0000000000001000ull
-#endif
-#ifndef BIT13
-  #define BIT13       0x0000000000002000ull
-#endif
-#ifndef BIT14
-  #define BIT14       0x0000000000004000ull
-#endif
-#ifndef BIT15
-  #define BIT15       0x0000000000008000ull
-#endif
-#ifndef BIT16
-  #define BIT16       0x0000000000010000ull
-#endif
-#ifndef BIT17
-  #define BIT17       0x0000000000020000ull
-#endif
-#ifndef BIT18
-  #define BIT18       0x0000000000040000ull
-#endif
-#ifndef BIT19
-  #define BIT19       0x0000000000080000ull
-#endif
-#ifndef BIT20
-  #define BIT20       0x0000000000100000ull
-#endif
-#ifndef BIT21
-  #define BIT21       0x0000000000200000ull
-#endif
-#ifndef BIT22
-  #define BIT22       0x0000000000400000ull
-#endif
-#ifndef BIT23
-  #define BIT23       0x0000000000800000ull
-#endif
-#ifndef BIT24
-  #define BIT24       0x0000000001000000ull
-#endif
-#ifndef BIT25
-  #define BIT25       0x0000000002000000ull
-#endif
-#ifndef BIT26
-  #define BIT26       0x0000000004000000ull
-#endif
-#ifndef BIT27
-  #define BIT27       0x0000000008000000ull
-#endif
-#ifndef BIT28
-  #define BIT28       0x0000000010000000ull
-#endif
-#ifndef BIT29
-  #define BIT29       0x0000000020000000ull
-#endif
-#ifndef BIT30
-  #define BIT30       0x0000000040000000ull
-#endif
-#ifndef BIT31
-  #define BIT31       0x0000000080000000ull
-#endif
-#ifndef BIT32
-  #define BIT32       0x0000000100000000ull
-#endif
-#ifndef BIT33
-  #define BIT33       0x0000000200000000ull
-#endif
-#ifndef BIT34
-  #define BIT34       0x0000000400000000ull
-#endif
-#ifndef BIT35
-  #define BIT35       0x0000000800000000ull
-#endif
-#ifndef BIT36
-  #define BIT36       0x0000001000000000ull
-#endif
-#ifndef BIT37
-  #define BIT37       0x0000002000000000ull
-#endif
-#ifndef BIT38
-  #define BIT38       0x0000004000000000ull
-#endif
-#ifndef BIT39
-  #define BIT39       0x0000008000000000ull
-#endif
-#ifndef BIT40
-  #define BIT40       0x0000010000000000ull
-#endif
-#ifndef BIT41
-  #define BIT41       0x0000020000000000ull
-#endif
-#ifndef BIT42
-  #define BIT42       0x0000040000000000ull
-#endif
-#ifndef BIT43
-  #define BIT43       0x0000080000000000ull
-#endif
-#ifndef BIT44
-  #define BIT44       0x0000100000000000ull
-#endif
-#ifndef BIT45
-  #define BIT45       0x0000200000000000ull
-#endif
-#ifndef BIT46
-  #define BIT46       0x0000400000000000ull
-#endif
-#ifndef BIT47
-  #define BIT47       0x0000800000000000ull
-#endif
-#ifndef BIT48
-  #define BIT48       0x0001000000000000ull
-#endif
-#ifndef BIT49
-  #define BIT49       0x0002000000000000ull
-#endif
-#ifndef BIT50
-  #define BIT50       0x0004000000000000ull
-#endif
-#ifndef BIT51
-  #define BIT51       0x0008000000000000ull
-#endif
-#ifndef BIT52
-  #define BIT52       0x0010000000000000ull
-#endif
-#ifndef BIT53
-  #define BIT53       0x0020000000000000ull
-#endif
-#ifndef BIT54
-  #define BIT54       0x0040000000000000ull
-#endif
-#ifndef BIT55
-  #define BIT55       0x0080000000000000ull
-#endif
-#ifndef BIT56
-  #define BIT56       0x0100000000000000ull
-#endif
-#ifndef BIT57
-  #define BIT57       0x0200000000000000ull
-#endif
-#ifndef BIT58
-  #define BIT58       0x0400000000000000ull
-#endif
-#ifndef BIT59
-  #define BIT59       0x0800000000000000ull
-#endif
-#ifndef BIT60
-  #define BIT60       0x1000000000000000ull
-#endif
-#ifndef BIT61
-  #define BIT61       0x2000000000000000ull
-#endif
-#ifndef BIT62
-  #define BIT62       0x4000000000000000ull
-#endif
-#ifndef BIT63
-  #define BIT63       0x8000000000000000ull
-#endif
-#endif
diff --git a/src/southbridge/amd/cimx/sb800/AmdSbLib.h b/src/southbridge/amd/cimx/sb800/AmdSbLib.h
deleted file mode 100644
index 70c0b3e213..0000000000
--- a/src/southbridge/amd/cimx/sb800/AmdSbLib.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _AMD_SB_LIB_H_
-#define _AMD_SB_LIB_H_
-
-#include <console/vtxprintf.h>
-
-#pragma pack(push, 1)
-
-#define NUM_IMAGE_LOCATION   32
-
-//Entry Point Call
-typedef void (*CIM_IMAGE_ENTRY) (void *pConfig);
-
-//Hook Call
-
-typedef struct _CIMFILEHEADER
-{
-  unsigned int  AMDLogo;
-  unsigned long long  CreatorID;
-  unsigned int  Version1;
-  unsigned int  Version2;
-  unsigned int  Version3;
-  unsigned int  ModuleInfoOffset;
-  unsigned int  EntryPoint;
-  unsigned int  ImageBase;
-  unsigned int  RelocTableOffset;
-  unsigned int  ImageSize;
-  unsigned short  CheckSum;
-  unsigned char ImageType;
-  unsigned char Reserved2;
-} CIMFILEHEADER;
-
-#ifndef BIT0
-  #define BIT0 (1 << 0)
-#endif
-#ifndef BIT1
-  #define BIT1 (1 << 1)
-#endif
-#ifndef BIT2
-  #define BIT2 (1 << 2)
-#endif
-#ifndef BIT3
-  #define BIT3 (1 << 3)
-#endif
-#ifndef BIT4
-  #define BIT4 (1 << 4)
-#endif
-#ifndef BIT5
-  #define BIT5 (1 << 5)
-#endif
-#ifndef BIT6
-  #define BIT6 (1 << 6)
-#endif
-#ifndef BIT7
-  #define BIT7 (1 << 7)
-#endif
-#ifndef BIT8
-  #define BIT8 (1 << 8)
-#endif
-#ifndef BIT9
-  #define BIT9 (1 << 9)
-#endif
-#ifndef BIT10
-  #define BIT10 (1 << 10)
-#endif
-#ifndef BIT11
-  #define BIT11 (1 << 11)
-#endif
-#ifndef BIT12
-  #define BIT12 (1 << 12)
-#endif
-#ifndef BIT13
-  #define BIT13 (1 << 13)
-#endif
-#ifndef BIT14
-  #define BIT14 (1 << 14)
-#endif
-#ifndef BIT15
-  #define BIT15 (1 << 15)
-#endif
-#ifndef BIT16
-  #define BIT16 (1 << 16)
-#endif
-#ifndef BIT17
-  #define BIT17 (1 << 17)
-#endif
-#ifndef BIT18
-  #define BIT18 (1 << 18)
-#endif
-#ifndef BIT19
-  #define BIT19 (1 << 19)
-#endif
-#ifndef BIT20
-  #define BIT20 (1 << 20)
-#endif
-#ifndef BIT21
-  #define BIT21 (1 << 21)
-#endif
-#ifndef BIT22
-  #define BIT22 (1 << 22)
-#endif
-#ifndef BIT23
-  #define BIT23 (1 << 23)
-#endif
-#ifndef BIT24
-  #define BIT24 (1 << 24)
-#endif
-#ifndef BIT25
-  #define BIT25 (1 << 25)
-#endif
-#ifndef BIT26
-  #define BIT26 (1 << 26)
-#endif
-#ifndef BIT27
-  #define BIT27 (1 << 27)
-#endif
-#ifndef BIT28
-  #define BIT28 (1 << 28)
-#endif
-#ifndef BIT29
-  #define BIT29 (1 << 29)
-#endif
-#ifndef BIT30
-  #define BIT30 (1 << 30)
-#endif
-#ifndef BIT31
-  #define BIT31 (1 << 31)
-#endif
-
-#pragma pack(pop)
-
-typedef enum
-{
-  AccWidthUint8 = 0,
-  AccWidthUint16,
-  AccWidthUint32,
-} ACC_WIDTH;
-
-#define S3_SAVE  0x80
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
deleted file mode 100644
index 7ab2cc1c07..0000000000
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ /dev/null
@@ -1,210 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config SOUTHBRIDGE_AMD_CIMX_SB800
-	bool
-	default n
-	select HAVE_USBDEBUG_OPTIONS
-	select AMD_SB_CIMX
-	select HAVE_CF9_RESET
-	select HAVE_CF9_RESET_PREPARE
-	select SOC_AMD_COMMON
-	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
-	select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
-	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
-	select BOOT_DEVICE_SUPPORTS_WRITES
-
-if SOUTHBRIDGE_AMD_CIMX_SB800
-config ENABLE_IDE_COMBINED_MODE
-	bool "Enable SATA IDE combined mode"
-	default n
-	help
-	  If Combined Mode is enabled. IDE controller is exposed and
-	  SATA controller has control over Port0 through Port3,
-	  IDE controller has control over Port4 and Port5.
-
-	  If Combined Mode is disabled, IDE controller is hidden and
-	  SATA controller has full control of all 6 Ports when operating in non-IDE mode.
-
-config IDE_COMBINED_MODE
-	hex
-	default 0x0 if ENABLE_IDE_COMBINED_MODE
-	default 0x1 if !ENABLE_IDE_COMBINED_MODE
-
-choice
-	prompt "SATA Mode"
-	default SB800_SATA_AHCI
-	help
-	  Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
-	  The default is AHCI.
-
-config SB800_SATA_IDE
-	bool "NATIVE"
-	help
-	  NATIVE does not require a ROM.
-
-config SB800_SATA_AHCI
-	bool "AHCI"
-	help
-	  AHCI is the default and may work with or without AHCI ROM. It depends on the payload support.
-	  For example, seabios does not require the AHCI ROM.
-
-config SB800_SATA_RAID
-	bool "RAID"
-	help
-	  sb800 RAID mode must have the two required ROM files.
-
-endchoice
-
-config SB800_SATA_MODE
-	hex
-	depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI)
-	default 0x0 if SB800_SATA_IDE
-	default 0x1 if SB800_SATA_RAID
-	default 0x2 if SB800_SATA_AHCI
-
-config SB_SUPERIO_HWM
-	bool
-	default n
-
-if SB800_SATA_AHCI
-config AHCI_ROM_ID
-	string "AHCI device PCI IDs"
-	default "1002,4391"
-
-config SB800_AHCI_ROM
-	bool "Add a AHCI ROM"
-
-config AHCI_ROM_FILE
-	string "AHCI ROM path and filename"
-	depends on SB800_AHCI_ROM
-	default "site-local/sb800/ahci.bin"
-endif
-
-if SB800_SATA_RAID
-config RAID_ROM_ID
-	string "RAID device PCI IDs"
-	default "1002,4393"
-	help
-	  1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
-
-config RAID_ROM_FILE
-	string "RAID ROM path and filename"
-	depends on SB800_SATA_RAID
-	default "site-local/sb800/raid.bin"
-
-config RAID_MISC_ROM_FILE
-	string "RAID Misc ROM path and filename"
-	default "site-local/sb800/misc.bin"
-	depends on SB800_SATA_RAID
-
-config RAID_MISC_ROM_POSITION
-	hex "RAID Misc ROM Position"
-	default 0xFFF00000
-	depends on SB800_SATA_RAID
-	help
-	  The RAID ROM requires that the MISC ROM is located between the range
-	  0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
-	  The CONFIG_ROM_SIZE must larger than 0x100000.
-
-endif
-
-config SB800_IMC_FWM
-	bool "Add IMC firmware"
-	default n
-	select SPI_FLASH_HAS_VOLATILE_GROUP if SPI_FLASH
-	help
-	  Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.
-
-if SB800_IMC_FWM
-
-config SB800_IMC_FWM_FILE
-	string "IMC firmware path and filename"
-	default "3rdparty/blobs/southbridge/amd/sb800/imc.bin"
-
-choice
-	prompt "SB800 Firmware ROM Position"
-
-config SB800_FWM_AT_FFFA0000
-	bool "0xFFFA0000"
-	help
-	  The IMC and GEC ROMs requires a 'signature' located at one of several
-	  fixed locations in memory.  The location used shouldn't matter, just
-	  select an area that doesn't conflict with anything else.
-
-config SB800_FWM_AT_FFF20000
-	bool "0xFFF20000"
-	help
-	  The IMC and GEC ROMs requires a 'signature' located at one of several
-	  fixed locations in memory.  The location used shouldn't matter, just
-	  select an area that doesn't conflict with anything else.
-
-config SB800_FWM_AT_FFE20000
-	depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096 || BOARD_ROMSIZE_KB_2048
-	bool "0xFFE20000"
-	help
-	  The IMC and GEC ROMs requires a 'signature' located at one of several
-	  fixed locations in memory.  The location used shouldn't matter, just
-	  select an area that doesn't conflict with anything else.
-
-config SB800_FWM_AT_FFC20000
-	depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096
-	bool "0xFFC20000"
-	help
-	  The IMC and GEC ROMs requires a 'signature' located at one of several
-	  fixed locations in memory.  The location used shouldn't matter, just
-	  select an area that doesn't conflict with anything else.
-
-config SB800_FWM_AT_FF820000
-	depends on BOARD_ROMSIZE_KB_8192
-	bool "0xFF820000"
-	help
-	  The IMC and GEC ROMs requires a 'signature' located at one of several
-	  fixed locations in memory.  The location used shouldn't matter, just
-	  select an area that doesn't conflict with anything else.
-
-endchoice
-
-config SB800_FWM_POSITION
-	hex
-	default 0xFFFA0000 if SB800_FWM_AT_FFFA0000
-	default 0xFFF20000 if SB800_FWM_AT_FFF20000
-	default 0xFFE20000 if SB800_FWM_AT_FFE20000
-	default 0xFFC20000 if SB800_FWM_AT_FFC20000
-	default 0xFF820000 if SB800_FWM_AT_FF820000
-
-endif  #SB800_IMC_FWM
-
-config EHCI_BAR
-	hex
-	default 0xfef00000
-
-choice
-	prompt "Fan Control"
-	default SB800_NO_FAN_CONTROL
-	help
-	  Select the method of SB800 fan control to be used.  None would be
-	  for either fixed maximum speed fans connected to the SB800 or for
-	  an external chip controlling the fan speeds.  Manual control sets
-	  up the SB800 fan control registers.  IMC fan control uses the SB800
-	  IMC to actively control the fan speeds.
-
-config SB800_NO_FAN_CONTROL
-	bool "None"
-	help
-	  No SB800 Fan control - Do not set up the SB800 fan control registers.
-
-config SB800_MANUAL_FAN_CONTROL
-	bool "Manual"
-	help
-	  Configure the SB800 fan control registers in devicetree.cb.
-
-config SB800_IMC_FAN_CONTROL
-	bool "IMC Based"
-	depends on SB800_IMC_FWM
-	help
-	  Set up the SB800 to use the IMC based Fan controller.  This requires
-	  the IMC ROM from AMD.  Configure the registers in devicetree.cb.
-
-endchoice
-
-endif #SOUTHBRIDGE_AMD_CIMX_SB800
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
deleted file mode 100644
index 1ac69aede2..0000000000
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ /dev/null
@@ -1,88 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# SB800 Platform Files
-
-bootblock-y += bootblock.c
-
-romstage-y += cfg.c
-romstage-y += early.c
-romstage-y += smbus.c smbus_spd.c
-
-ramstage-y += cfg.c
-ramstage-y += late.c
-
-all-y += reset.c
-
-ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c
-ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c
-ramstage-$(CONFIG_SPI_FLASH) += spi.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
-
-postcar-y += ramtop.c
-romstage-y += ramtop.c
-ramstage-y += ramtop.c
-
-bootblock-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c
-romstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c
-ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c
-
-ramstage-y   += smbus.c
-ramstage-y   += lpc.c
-
-ifeq ($(CONFIG_SB800_SATA_AHCI), y)
-ifdef CONFIG_SB800_AHCI_ROM
-	stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID))
-	cbfs-files-y += pci$(stripped_ahci_rom_id).rom
-	pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE))
-	pci$(stripped_ahci_rom_id).rom-type := optionrom
-endif
-endif
-
-ifeq ($(CONFIG_SB800_SATA_RAID), y)
-	stripped_raid_rom_id = $(call strip_quotes,$(CONFIG_RAID_ROM_ID))
-	cbfs-files-y += pci$(stripped_raid_rom_id).rom
-	pci$(stripped_raid_rom_id).rom-file := $(call strip_quotes,$(CONFIG_RAID_ROM_FILE))
-	pci$(stripped_raid_rom_id).rom-type := optionrom
-
-	cbfs-files-y += raid/misc.bin
-	raid/misc.bin-file := $(call strip_quotes,$(CONFIG_RAID_MISC_ROM_FILE))
-	raid/misc.bin-position := $(CONFIG_RAID_MISC_ROM_POSITION)
-	raid/misc.bin-type := raw
-endif
-
-ifeq ($(CONFIG_SB800_IMC_FWM), y)
-
-# ROMSIG At ROMBASE + 0x20000:
-# +-----------+---------------+----------------+------------+
-# |0x55AA55AA |EC ROM Address |GEC ROM Address |            |
-# +-----------+---------------+----------------+------------+
-# EC ROM should be 64K aligned.
-SB800_FWM_POSITION=$(shell printf %u $(CONFIG_SB800_FWM_POSITION))
-#assume the cbfs header is less than 128 bytes.
-ROMSIG_SIZE=16
-
-SB800_IMC_POSITION=$(call int-align,$(call add-int,$(SB800_FWM_POSITION) $(ROMSIG_SIZE) 128),65536)
-
-$(obj)/coreboot_SB800_romsig.bin: \
-			$(call strip_quotes, $(CONFIG_SB800_IMC_FWM_FILE)) \
-			$(obj)/config.h \
-			$(obj)/mainboard/$(MAINBOARDDIR)/static.c
-	echo "    SB800 FW  $@"
-	for fwm in 1437226410 \
-		$(SB800_IMC_POSITION) \
-		0 \
-		0 ; do \
-		echo  $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \
-	done > $@
-
-cbfs-files-y += SB800/fwm
-SB800/fwm-file := $(obj)/coreboot_SB800_romsig.bin
-SB800/fwm-position := $(SB800_FWM_POSITION)
-SB800/fwm-type := raw
-
-cbfs-files-y += SB800/imc
-SB800/imc-file := $(call strip_quotes, $(CONFIG_SB800_IMC_FWM_FILE))
-SB800/imc-position := $(SB800_IMC_POSITION)
-SB800/imc-type := raw
-
-endif
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
deleted file mode 100644
index 760088632e..0000000000
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _AMD_SBPLATFORM_H_
-#define _AMD_SBPLATFORM_H_
-
-#include <stddef.h>
-
-typedef unsigned long long PLACEHOLDER;
-
-#ifndef SBOEM_ACPI_RESTORE_SWSMI
-  #define SBOEM_BEFORE_PCI_RESTORE_SWSMI    0xD3
-  #define SBOEM_AFTER_PCI_RESTORE_SWSMI     0xD4
-#endif
-
-#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
-
-/*
-/// Extended PCI Address
-typedef struct _EXT_PCI_ADDR {
-  UINT32                  Reg :16; ///< / PCI Register
-  UINT32                  Func:3;  ///< / PCI Function
-  UINT32                  Dev :5;  ///< / PCI Device
-  UINT32                  Bus :8;  ///< / PCI Address
-} EXT_PCI_ADDR;
-
-/// PCI Address
-typedef union _PCI_ADDR {
-  UINT32                  ADDR; ///< / 32 bit Address
-  EXT_PCI_ADDR            Addr; ///< / Extended PCI Address
-} PCI_ADDR;
-*/
-#endif
-#define FIXUP_PTR(ptr)  ptr
-
-#if CONFIG(SB800_IMC_FWM)
-	#define IMC_ENABLE_OVER_WRITE        0x01
-#endif
-
-#include "AmdSbLib.h"
-#include "Amd.h"
-#include <SB800.h>
-#include <SBTYPE.h>
-#include <ACPILIB.h>
-#include <SBDEF.h>
-#include <AMDSBLIB.h>
-#include <SBSUBFUN.h>
-#include "platform_cfg.h"
-#include <OEM.h>
-#include <AMD.h>
-
-//------------------------------------------------------------------------------------------------------------------------//
-/**
- * SB_CIMx_PARAMETER                0                1                   2            Default Value When CIMx Take over
- *  SpreadSpectrum         CIMx take over   User (Setup Option) User (Setup Option)               Enable
- * SpreadSpectrumType      CIMx take over   User (Setup Option) User (Setup Option)               Normal
- *     HpetTimer           CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *     HpetMsiDis          CIMx take over   User (Setup Option) User (Setup Option)               Enable (0x00)
- *      IrConfig           CIMx take over   User (Setup Option) User (Setup Option)               Disable (0x00)
- * SpiFastReadEnable       CIMx take over   User (Setup Option) User (Setup Option)               Disable
- * SpiFastReadSpeed        CIMx take over   User (Setup Option) User (Setup Option)               Disable (NULL)
- *     NbSbGen2            CIMx take over   User (Setup Option) User (Setup Option)               Enable
- * AlinkPhyPllPowerDown    CIMx take over   User (Setup Option) User (Setup Option)               Enable
- * ResetCpuOnSyncFlood     CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *     GppGen2             CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  GppMemWrImprove        CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *    GppPortAspm          CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  GppLaneReversal        CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  GppPhyPllPowerDown     CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *  UsbPhyPowerDown        CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  SBGecDebugBus          CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *     SBGecPwr            CIMx take over   User (Setup Option) User (Setup Option)               Never Power down (0x11)
- *   SataSetMaxGen2        CIMx take over   User (Setup Option) User (Setup Option)               Max Gen3 (0x00)
- *   SataClkMode           CIMx take over   User (Setup Option) User (Setup Option)               0x90   int. 100Mhz
- *  SataAggrLinkPmCap      CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *  SataPortMultCap        CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *   SataPscCap            CIMx take over   User (Setup Option) User (Setup Option)               Enable (0x00)
- *   SataSscCap            CIMx take over   User (Setup Option) User (Setup Option)               Enable (0x00)
- * SataFisBasedSwitching   CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *   SataCccSupport        CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *   SataMsiCapability     CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *   SataClkAutoOff        CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *    AcDcMsg              CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *   TimerTickTrack        CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  ClockInterruptTag      CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  OhciTrafficHanding     CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  EhciTrafficHanding     CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  FusionMsgCMultiCore    CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *   FusionMsgCStage       CIMx take over   User (Setup Option) User (Setup Option)               Disable
- */
-#define SB_CIMx_PARAMETER  0x02
-
-// Generic
-#define cimSpreadSpectrumDefault        TRUE
-#define cimSpreadSpectrumTypeDefault	0x00      // Normal
-#define cimHpetTimerDefault             TRUE
-#define cimHpetMsiDisDefault            FALSE     // Enable
-#define cimIrConfigDefault              0x00      // Disable
-#define cimSpiFastReadEnableDefault     0x01      // Enable
-#define cimSpiFastReadSpeedDefault      0x01      // 33 MHz
-#define cimSioHwmPortEnableDefault      FALSE
-// GPP/AB Controller
-#define cimNbSbGen2Default              TRUE
-#define cimAlinkPhyPllPowerDownDefault  TRUE
-#define cimResetCpuOnSyncFloodDefault   TRUE
-#define cimGppGen2Default               FALSE
-#define cimGppMemWrImproveDefault       TRUE
-#define cimGppPortAspmDefault           FALSE
-#define cimGppLaneReversalDefault       FALSE
-#define cimGppPhyPllPowerDownDefault    TRUE
-// USB Controller
-#define cimUsbPhyPowerDownDefault       FALSE
-// GEC Controller
-#define cimSBGecDebugBusDefault         FALSE
-#define cimSBGecPwrDefault              0x03
-// Sata Controller
-#define cimSataSetMaxGen2Default        0x00
-#define cimSATARefClkSelDefault         0x10
-#define cimSATARefDivSelDefault         0x80
-#define cimSataAggrLinkPmCapDefault     TRUE
-#define cimSataPortMultCapDefault       TRUE
-#define cimSataPscCapDefault            0x00      // Enable
-#define cimSataSscCapDefault            0x00      // Enable
-#define cimSataFisBasedSwitchingDefault FALSE
-#define cimSataCccSupportDefault        FALSE
-#define cimSataClkAutoOffDefault        FALSE
-#define cimNativepciesupportDefault     FALSE
-// Fusion Related
-#define cimAcDcMsgDefault               FALSE
-#define cimTimerTickTrackDefault        FALSE
-#define cimClockInterruptTagDefault     FALSE
-#define cimOhciTrafficHandingDefault    FALSE
-#define cimEhciTrafficHandingDefault    FALSE
-#define cimFusionMsgCMultiCoreDefault   FALSE
-#define cimFusionMsgCStageDefault       FALSE
-
-#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
-#include <spi-generic.h>
-
-#define BIOSRAM_INDEX	0xcd4
-#define BIOSRAM_DATA	0xcd5
-
-#endif // _AMD_SBPLATFORM_H_
diff --git a/src/southbridge/amd/cimx/sb800/acpi/audio.asl b/src/southbridge/amd/cimx/sb800/acpi/audio.asl
deleted file mode 100644
index 0d5f00d33c..0000000000
--- a/src/southbridge/amd/cimx/sb800/acpi/audio.asl
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device(AZHD) {	/* 0:14.2 - HD Audio */
-	Name(_ADR, 0x00140002)
-	OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
-		Field(AZPD, AnyAcc, NoLock, Preserve) {
-		offset (0x42),
-		NSDI, 1,
-		NSDO, 1,
-		NSEN, 1,
-		offset (0x44),
-		IPCR, 4,
-		offset (0x54),
-		PWST, 2,
-		, 6,
-		PMEB, 1,
-		, 6,
-		PMST, 1,
-		offset (0x62),
-		MMCR, 1,
-		offset (0x64),
-		MMLA, 32,
-		offset (0x68),
-		MMHA, 32,
-		offset (0x6C),
-		MMDT, 16,
-	}
-} /* end AZHD */
diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
deleted file mode 100644
index 5527660255..0000000000
--- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl
+++ /dev/null
@@ -1,166 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* System Bus */
-/*  _SB.PCI0 */
-
-/* Operating System Capabilities Method */
-Method(_OSC,4)
-{
-	/* Check for proper PCI/PCIe UUID */
-	If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
-	{
-		/* Let OS control everything */
-		Return (Arg3)
-	} Else {
-		CreateDWordField(Arg3,0,CDW1)
-		CDW1 |= 4	// Unrecognized UUID
-		Return (Arg3)
-	}
-}
-
-Method(_BBN, 0) { /* Bus number = 0 */
-	Return (0)
-}
-Method(_STA, 0) {
-	/* DBGO("\\_SB\\PCI0\\_STA\n") */
-	Return (0x0b)     /* Status is visible */
-}
-
-Method(_PRT,0) {
-	If(PICM){ Return(APR0) }   /* APIC mode */
-	Return (PR0)                  /* PIC Mode */
-} /* end _PRT */
-
-/* Describe the Southbridge devices */
-
-#include "pcie.asl"
-
-Device(STCR) {
-	Name(_ADR, 0x00110000)
-	#include "acpi/sata.asl"
-} /* end STCR */
-
-#include "usb.asl"
-
-Device(SBUS) {
-	Name(_ADR, 0x00140000)
-} /* end SBUS */
-
-#include "audio.asl"
-
-#include "lpc.asl"
-
-/* PCI bridge */
-Device(PIBR) {
-	Name(_ADR, 0x00140004)
-	Name(_PRW, Package() {0x18, 4})
-
-	Method(_PRT, 0) {
-		Return (PCIB)
-	}
-} /* end HostPciBr */
-
-Device(ACAD) {
-	Name(_ADR, 0x00140005)
-} /* end Ac97audio */
-
-Device(ACMD) {
-	Name(_ADR, 0x00140006)
-} /* end Ac97modem */
-
-Name(CRES, ResourceTemplate() {
-	/* Set the Bus number and Secondary Bus number for the PCI0 device
-	 * The Secondary bus range for PCI0 lets the system
-	 * know what bus values are allowed on the downstream
-	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI buses can have 256 secondary buses which
-	 * range from [0-0xFF] but they do not need to be
-	 * sequential.
-	 */
-	WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-		0x0000,		/* address granularity */
-		0x0000,		/* range minimum */
-		0x00FF,		/* range maximum */
-		0x0000,		/* translation */
-		0x0100,		/* length */
-		,, PSB0)		/* ResourceSourceIndex, ResourceSource, DescriptorName */
-
-	IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
-
-	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000,		/* address granularity */
-		0x0000,		/* range minimum */
-		0x0CF7,		/* range maximum */
-		0x0000,		/* translation */
-		0x0CF8		/* length */
-	)
-
-	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000,		/* address granularity */
-		0x0D00,		/* range minimum */
-		0xFFFF,		/* range maximum */
-		0x0000,		/* translation */
-		0xF300		/* length */
-	)
-
-	Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)	/* VGA memory space */
-
-	/* memory space for PCI BARs below 4GB */
-	Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
-}) /* End Name(_SB.PCI0.CRES) */
-
-Method(_CRS, 0) {
-	/* DBGO("\\_SB\\PCI0\\_CRS\n") */
-	CreateDWordField(CRES, ^MMIO._BAS, MM1B)
-	CreateDWordField(CRES, ^MMIO._LEN, MM1L)
-
-	/*
-	 * Declare memory between TOM1 and 4GB as available
-	 * for PCI MMIO.
-	 * Use ShiftLeft to avoid 64bit constant (for XP).
-	 * This will work even if the OS does 32bit arithmetic, as
-	 * 32bit (0x00000000 - TOM1) will wrap and give the same
-	 * result as 64bit (0x100000000 - TOM1).
-	 */
-	MM1B = TOM1
-	Local0 = 0x10000000 << 4
-	Local0 -= TOM1
-	MM1L = Local0
-
-	Return (CRES) /* note to change the Name buffer */
-} /* end of Method(_SB.PCI0._CRS) */
-
-/*
- *
- *               FIRST METHOD CALLED UPON BOOT
- *
- *  1. If debugging, print current OS and ACPI interpreter.
- *  2. Get PCI Interrupt routing from ACPI VSM, this
- *     value is based on user choice in BIOS setup.
- */
-Method(_INI, 0) {
-	/* DBGO("\\_SB\\_INI\n") */
-	/* DBGO("   DSDT.ASL code from ") */
-	/* DBGO(__DATE__) */
-	/* DBGO(" ") */
-	/* DBGO(__TIME__) */
-	/* DBGO("\n   Sleep states supported: ") */
-	/* DBGO("\n") */
-	/* DBGO("   \\_OS=") */
-	/* DBGO(\_OS) */
-	/* DBGO("\n   \\_REV=") */
-	/* DBGO(\_REV) */
-	/* DBGO("\n") */
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\SBRI <= 0x13) {
-	*	\PWDE = 0
-	* }
-	*/
-} /* End Method(_SB._INI) */
-
-Scope(\){
-
-	#include "misc_io.asl"
-
-}
diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
deleted file mode 100644
index 151b015074..0000000000
--- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* 0:14.3 - LPC */
-Device(LIBR) {
-	Name(_ADR, 0x00140003)
-
-	/* Real Time Clock Device */
-	Device(RTC0) {
-		Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
-		Name(_CRS, ResourceTemplate() {
-			IRQNoFlags(){8}
-			IO(Decode16,0x0070, 0x0070, 0, 2)
-		})
-	} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
-	Device(TMR) {	/* Timer */
-		Name(_HID,EISAID("PNP0100"))	/* System Timer */
-		Name(_CRS, ResourceTemplate() {
-			IRQNoFlags(){0}
-			IO(Decode16, 0x0040, 0x0040, 0, 4)
-		})
-	} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
-	Device(SPKR) {	/* Speaker */
-		Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
-		Name(_CRS, ResourceTemplate() {
-			IO(Decode16, 0x0061, 0x0061, 0, 1)
-		})
-	} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
-	Device(PIC) {
-		Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
-		Name(_CRS, ResourceTemplate() {
-			IRQNoFlags(){2}
-			IO(Decode16,0x0020, 0x0020, 0, 2)
-			IO(Decode16,0x00A0, 0x00A0, 0, 2)
-		})
-	} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
-	Device(MAD) { /* 8257 DMA */
-		Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
-		Name(_CRS, ResourceTemplate() {
-			DMA(Compatibility,BusMaster,Transfer8){4}
-			IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
-			IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
-			IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
-			IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
-			IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
-			IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
-		}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
-	} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
-	Device(COPR) {
-		Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
-		Name(_CRS, ResourceTemplate() {
-			IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
-			IRQNoFlags(){13}
-		})
-	} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-	#include "acpi/superio.asl"
-} /* end LIBR */
diff --git a/src/southbridge/amd/cimx/sb800/acpi/misc_io.asl b/src/southbridge/amd/cimx/sb800/acpi/misc_io.asl
deleted file mode 100644
index b8296fb066..0000000000
--- a/src/southbridge/amd/cimx/sb800/acpi/misc_io.asl
+++ /dev/null
@@ -1,171 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-
-/* Client Management index/data registers */
-OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
-	Field(CMT, ByteAcc, NoLock, Preserve) {
-	CMTI,      8,
-	/* Client Management Data register */
-	G64E,   1,
-	G64O,      1,
-	G32O,      2,
-	,       2,
-	GPSL,     2,
-}
-
-/* GPM Port register */
-OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
-	Field(GPT, ByteAcc, NoLock, Preserve) {
-	GPB0,1,
-	GPB1,1,
-	GPB2,1,
-	GPB3,1,
-	GPB4,1,
-	GPB5,1,
-	GPB6,1,
-	GPB7,1,
-}
-
-/* Flash ROM program enable register */
-OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
-	Field(FRE, ByteAcc, NoLock, Preserve) {
-	,     0x00000006,
-	FLRE, 0x00000001,
-}
-
-/* PM2 index/data registers */
-OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
-	Field(PM2R, ByteAcc, NoLock, Preserve) {
-	PM2I, 0x00000008,
-	PM2D, 0x00000008,
-}
-
-/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
-OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
-	Field(PIOR, ByteAcc, NoLock, Preserve) {
-	PIOI, 0x00000008,
-	PIOD, 0x00000008,
-}
-IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
-	    , 1,	/* MiscControl */
-	T1EE, 1,
-	T2EE, 1,
-	Offset(0x01),	/* MiscStatus */
-	, 1,
-	T1E, 1,
-	T2E, 1,
-	Offset(0x04),	/* SmiWakeUpEventEnable3 */
-	, 7,
-	SSEN, 1,
-	Offset(0x07),	/* SmiWakeUpEventStatus3 */
-	, 7,
-	CSSM, 1,
-	Offset(0x10),	/* AcpiEnable */
-	, 6,
-	PWDE, 1,
-	Offset(0x1C),	/* ProgramIoEnable */
-	, 3,
-	MKME, 1,
-	IO3E, 1,
-	IO2E, 1,
-	IO1E, 1,
-	IO0E, 1,
-	Offset(0x1D),	/* IOMonitorStatus */
-	, 3,
-	MKMS, 1,
-	IO3S, 1,
-	IO2S, 1,
-	IO1S, 1,
-	IO0S,1,
-	Offset(0x20),	/* AcpiPmEvtBlk. TODO: should be 0x60 */
-	APEB, 16,
-	Offset(0x36),	/* GEvtLevelConfig */
-	, 6,
-	ELC6, 1,
-	ELC7, 1,
-	Offset(0x37),	/* GPMLevelConfig0 */
-	, 3,
-	PLC0, 1,
-	PLC1, 1,
-	PLC2, 1,
-	PLC3, 1,
-	PLC8, 1,
-	Offset(0x38),	/* GPMLevelConfig1 */
-	, 1,
-	 PLC4, 1,
-	 PLC5, 1,
-	, 1,
-	 PLC6, 1,
-	 PLC7, 1,
-	Offset(0x3B),	/* PMEStatus1 */
-	GP0S, 1,
-	GM4S, 1,
-	GM5S, 1,
-	APS, 1,
-	GM6S, 1,
-	GM7S, 1,
-	GP2S, 1,
-	STSS, 1,
-	Offset(0x55),	/* SoftPciRst */
-	SPRE, 1,
-	, 1,
-	, 1,
-	PNAT, 1,
-	PWMK, 1,
-	PWNS, 1,
-
-	Offset(0x65),	/* UsbPMControl */
-	, 4,
-	URRE, 1,
-	Offset(0x68),	/* MiscEnable68 */
-	, 3,
-	TMTE, 1,
-	, 1,
-	Offset(0x92),	/* GEVENTIN */
-	, 7,
-	E7IS, 1,
-	Offset(0x96),	/* GPM98IN */
-	G8IS, 1,
-	G9IS, 1,
-	Offset(0x9A),	/* EnhanceControl */
-	,7,
-	HPDE, 1,
-	Offset(0xA8),	/* PIO7654Enable */
-	IO4E, 1,
-	IO5E, 1,
-	IO6E, 1,
-	IO7E, 1,
-	Offset(0xA9),	/* PIO7654Status */
-	IO4S, 1,
-	IO5S, 1,
-	IO6S, 1,
-	IO7S, 1,
-}
-
-/* PM1 Event Block
-* First word is PM1_Status, Second word is PM1_Enable
-*/
-OperationRegion(P1EB, SystemIO, APEB, 0x04)
-	Field(P1EB, ByteAcc, NoLock, Preserve) {
-	TMST, 1,
-	,    3,
-	BMST,    1,
-	GBST,   1,
-	Offset(0x01),
-	PBST, 1,
-	, 1,
-	RTST, 1,
-	, 3,
-	PWST, 1,
-	SPWS, 1,
-	Offset(0x02),
-	TMEN, 1,
-	, 4,
-	GBEN, 1,
-	Offset(0x03),
-	PBEN, 1,
-	, 1,
-	RTEN, 1,
-	, 3,
-	PWDA, 1,
-}
diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl
deleted file mode 100644
index f69ba1db24..0000000000
--- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl
+++ /dev/null
@@ -1,481 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\) {
-	/* PCI IRQ mapping registers, C00h-C01h. */
-	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
-		Field(PRQM, ByteAcc, NoLock, Preserve) {
-		PRQI, 0x00000008,
-		PRQD, 0x00000008,  /* Offset: 1h */
-	}
-	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
-		PIRA, 0x00000008,	/* Index 0 */
-		PIRB, 0x00000008,	/* Index 1 */
-		PIRC, 0x00000008,	/* Index 2 */
-		PIRD, 0x00000008,	/* Index 3 */
-		PIRE, 0x00000008,	/* Index 4 */
-		PIRF, 0x00000008,	/* Index 5 */
-		PIRG, 0x00000008,	/* Index 6 */
-		PIRH, 0x00000008,	/* Index 7 */
-	}
-
-	/* PCI Error control register */
-	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
-		Field(PERC, ByteAcc, NoLock, Preserve) {
-		SENS, 0x00000001,
-		PENS, 0x00000001,
-		SENE, 0x00000001,
-		PENE, 0x00000001,
-	}
-}
-
-Scope(\_SB) {
-	Field(PCFG, ByteAcc, NoLock, Preserve) {
-		/* Byte offsets are computed using the following technique:
-		 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
-		 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
-		*/
-		Offset(0x00088024),	/* SATA reg 24h Bus 0, Device 17, Function 0 */
-		STB5, 32,
-		Offset(0x00098042),	/* OHCI0 reg 42h - Bus 0, Device 19, Function 0 */
-		PT0D, 1,
-		PT1D, 1,
-		PT2D, 1,
-		PT3D, 1,
-		PT4D, 1,
-		PT5D, 1,
-		PT6D, 1,
-		PT7D, 1,
-		PT8D, 1,
-		PT9D, 1,
-		Offset(0x000A0004),	/* SMBUS reg 4h - Bus 0, Device 20, Function 0 */
-		SBIE, 1,
-		SBME, 1,
-		Offset(0x000A0008),	/* SMBUS reg 8h - Bus 0, Device 20, Function 0 */
-		SBRI, 8,
-		Offset(0x000A0014),	/* SMBUS reg 14h - Bus 0, Device 20, Function 0 */
-		SBB1, 32,
-		Offset(0x000A0078),	/* SMBUS reg 78h - Bus 0, Device 20, Function 0 */
-		,14,
-		P92E, 1,		/* Port92 decode enable */
-	}
-
-	OperationRegion(SB5, SystemMemory, STB5, 0x1000)
-		Field(SB5, AnyAcc, NoLock, Preserve){
-		/* Port 0 */
-		Offset(0x120),		/* Port 0 Task file status */
-		P0ER, 1,
-		, 2,
-		P0DQ, 1,
-		, 3,
-		P0BY, 1,
-		Offset(0x128),		/* Port 0 Serial ATA status */
-		P0DD, 4,
-		, 4,
-		P0IS, 4,
-		Offset(0x12C),		/* Port 0 Serial ATA control */
-		P0DI, 4,
-		Offset(0x130),		/* Port 0 Serial ATA error */
-		, 16,
-		P0PR, 1,
-
-		/* Port 1 */
-		offset(0x1A0),		/* Port 1 Task file status */
-		P1ER, 1,
-		, 2,
-		P1DQ, 1,
-		, 3,
-		P1BY, 1,
-		Offset(0x1A8),		/* Port 1 Serial ATA status */
-		P1DD, 4,
-		, 4,
-		P1IS, 4,
-		Offset(0x1AC),		/* Port 1 Serial ATA control */
-		P1DI, 4,
-		Offset(0x1B0),		/* Port 1 Serial ATA error */
-		, 16,
-		P1PR, 1,
-
-		/* Port 2 */
-		Offset(0x220),		/* Port 2 Task file status */
-		P2ER, 1,
-		, 2,
-		P2DQ, 1,
-		, 3,
-		P2BY, 1,
-		Offset(0x228),		/* Port 2 Serial ATA status */
-		P2DD, 4,
-		, 4,
-		P2IS, 4,
-		Offset(0x22C),		/* Port 2 Serial ATA control */
-		P2DI, 4,
-		Offset(0x230),		/* Port 2 Serial ATA error */
-		, 16,
-		P2PR, 1,
-
-		/* Port 3 */
-		Offset(0x2A0),		/* Port 3 Task file status */
-		P3ER, 1,
-		, 2,
-		P3DQ, 1,
-		, 3,
-		P3BY, 1,
-		Offset(0x2A8),		/* Port 3 Serial ATA status */
-		P3DD, 4,
-		, 4,
-		P3IS, 4,
-		Offset(0x2AC),		/* Port 3 Serial ATA control */
-		P3DI, 4,
-		Offset(0x2B0),		/* Port 3 Serial ATA error */
-		, 16,
-		P3PR, 1,
-	}
-
-		Name(IRQB, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Shared){15}
-		})
-
-		Name(IRQP, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
-		})
-
-		Name(PITF, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){9}
-		})
-
-		Device(INTA) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 1)
-
-			Method(_STA, 0) {
-				if (PIRA) {
-					Return (0x0b) /* sata is invisible */
-				} else {
-					Return (0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTA._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
-				PIRA = 0
-			} /* End Method(_SB.INTA._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
-				Return (IRQP)
-			} /* Method(_SB.INTA._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				IRQN = 1 << PIRA
-				Return (IRQB)
-			} /* Method(_SB.INTA._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKA\\_SRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Local0--
-				}
-				PIRA = Local0
-			} /* End Method(_SB.INTA._SRS) */
-		} /* End Device(INTA) */
-
-		Device(INTB) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 2)
-
-			Method(_STA, 0) {
-				if (PIRB) {
-					Return (0x0b) /* sata is invisible */
-				} else {
-					Return (0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTB._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
-				PIRB = 0
-			} /* End Method(_SB.INTB._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
-				Return (IRQP)
-			} /* Method(_SB.INTB._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				IRQN = 1 << PIRB
-				Return (IRQB)
-			} /* Method(_SB.INTB._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Local0--
-				}
-				PIRB = Local0
-			} /* End Method(_SB.INTB._SRS) */
-		} /* End Device(INTB)  */
-
-		Device(INTC) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 3)
-
-			Method(_STA, 0) {
-				if (PIRC) {
-					Return (0x0b) /* sata is invisible */
-				} else {
-					Return (0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTC._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
-				PIRC = 0
-			} /* End Method(_SB.INTC._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTC._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				IRQN = 1 << PIRC
-				Return (IRQB)
-			} /* Method(_SB.INTC._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Local0--
-				}
-				PIRC = Local0
-			} /* End Method(_SB.INTC._SRS) */
-		} /* End Device(INTC)  */
-
-		Device(INTD) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 4)
-
-			Method(_STA, 0) {
-				if (PIRD) {
-					Return (0x0b) /* sata is invisible */
-				} else {
-					Return (0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTD._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
-				PIRD = 0
-			} /* End Method(_SB.INTD._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
-				Return (IRQP)
-			} /* Method(_SB.INTD._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				IRQN = 1 << PIRD
-				Return (IRQB)
-			} /* Method(_SB.INTD._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Local0--
-				}
-				PIRD = Local0
-			} /* End Method(_SB.INTD._SRS) */
-		} /* End Device(INTD)  */
-
-		Device(INTE) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 5)
-
-			Method(_STA, 0) {
-				if (PIRE) {
-					Return (0x0b) /* sata is invisible */
-				} else {
-					Return (0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTE._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
-				PIRE = 0
-			} /* End Method(_SB.INTE._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
-				Return (IRQP)
-			} /* Method(_SB.INTE._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				IRQN = 1 << PIRE
-				Return (IRQB)
-			} /* Method(_SB.INTE._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Local0--
-				}
-				PIRE = Local0
-			} /* End Method(_SB.INTE._SRS) */
-		} /* End Device(INTE)  */
-
-		Device(INTF) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 6)
-
-			Method(_STA, 0) {
-				if (PIRF) {
-					Return (0x0b) /* sata is invisible */
-				} else {
-					Return (0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTF._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
-				PIRF = 0
-			} /* End Method(_SB.INTF._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
-				Return (PITF)
-			} /* Method(_SB.INTF._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				IRQN = 1 << PIRF
-				Return (IRQB)
-			} /* Method(_SB.INTF._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Local0--
-				}
-				PIRF = Local0
-			} /*  End Method(_SB.INTF._SRS) */
-		} /* End Device(INTF)  */
-
-		Device(INTG) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 7)
-
-			Method(_STA, 0) {
-				if (PIRG) {
-					Return (0x0b) /* sata is invisible */
-				} else {
-					Return (0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTG._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
-				PIRG = 0
-			} /* End Method(_SB.INTG._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
-				Return (IRQP)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				IRQN = 1 << PIRG
-				Return (IRQB)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Local0--
-				}
-				PIRG = Local0
-			} /* End Method(_SB.INTG._SRS)  */
-		} /* End Device(INTG)  */
-
-		Device(INTH) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 8)
-
-			Method(_STA, 0) {
-				if (PIRH) {
-					Return (0x0b) /* sata is invisible */
-				} else {
-					Return (0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTH._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
-				PIRH = 0
-			} /* End Method(_SB.INTH._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
-				Return (IRQP)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				IRQN = 1 << PIRH
-				Return (IRQB)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Local0--
-				}
-				PIRH = Local0
-			} /* End Method(_SB.INTH._SRS)  */
-		} /* End Device(INTH)   */
-
-	}   /* End Scope(_SB)  */
diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl
deleted file mode 100644
index b81c5b1c37..0000000000
--- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* SMBUS Support */
-Mutex (SBX0, 0x00)
-OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
-	Field (SMB0, ByteAcc, NoLock, Preserve) {
-		HSTS,   8,  /* SMBUS status */
-		SSTS,   8,  /* SMBUS slave status */
-		HCNT,   8,  /* SMBUS control */
-		HCMD,   8,  /* SMBUS host cmd */
-		HADD,   8,  /* SMBUS address */
-		DAT0,   8,  /* SMBUS data0 */
-		DAT1,   8,  /* SMBUS data1 */
-		BLKD,   8,  /* SMBUS block data */
-		SCNT,   8,  /* SMBUS slave control */
-		SCMD,   8,  /* SMBUS shadow cmd */
-		SEVT,   8,  /* SMBUS slave event */
-		SDAT,   8   /* SMBUS slave data */
-}
-
-Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
-	HSTS = 0x1e
-	Local0 = 0xfa
-	While ((HSTS & 0x1e) != 0) && (Local0 > 0)) {
-		Stall (0x64)
-		Local0--
-	}
-
-	Return (Local0)
-}
-
-Method (SWTC, 1, NotSerialized) {
-	Local0 = Arg0
-	Local2 = 0x07
-	Local1 = 1
-	While (Local1 == 1) {
-		Local3 = HSTS & 0x1e
-		If (Local3 != 0) { /* read success */
-			If (Local3 != 0x02) {
-				Local2 = 0
-			}
-
-			Local1 = 0
-		}
-		Else {
-			If (Local0 < 0x0A) { /* read failure */
-				Local2 = 0x10
-				Local1 = 0
-			}
-			Else {
-				Sleep (0x0A) /* 10 ms, try again */
-				Local0 -= 0x0a
-			}
-		}
-	}
-
-	Return (Local2)
-}
-
-Method (SMBR, 3, NotSerialized) {
-	Local0 = 0x07
-	If (Acquire (SBX0, 0xFFFF) == 0) {
-		Local0 = WCLR () /* clear SMBUS status register before read data */
-		If (Local0 == 0) {
-			Release (SBX0)
-			Return (0x0)
-		}
-
-		HSTS = 0x1f
-		HADD = (Arg1 << 1) | 1
-		HCMD = Arg2
-		If (Arg0 == 0x07) {
-			HCNT = 0x48 /* read byte */
-		}
-
-		Local1 = SWTC (0x03E8) /* 1000 ms */
-		If (Local1 == 0) {
-			If (Arg0 == 0x07) {
-				Local0 = DAT0
-			}
-		}
-		Else {
-			Local0 = Local1
-		}
-
-		Release (SBX0)
-	}
-
-	/* DBGO("the value of SMBusData0 register ") */
-	/* DBGO(Arg2) */
-	/* DBGO(" is ") */
-	/* DBGO(Local0) */
-	/* DBGO("\n") */
-
-	Return (Local0)
-}
diff --git a/src/southbridge/amd/cimx/sb800/acpi/usb.asl b/src/southbridge/amd/cimx/sb800/acpi/usb.asl
deleted file mode 100644
index 35c8c7e459..0000000000
--- a/src/southbridge/amd/cimx/sb800/acpi/usb.asl
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* 0:12.0 - OHCI */
-Device(UOH1) {
-	Name(_ADR, 0x00120000)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH1 */
-
-/* 0:12.2 - EHCI */
-Device(UOH2) {
-	Name(_ADR, 0x00120002)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH2 */
-
-/* 0:13.0 - OHCI */
-Device(UOH3) {
-	Name(_ADR, 0x00130000)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH3 */
-
-/* 0:13.2 - EHCI */
-Device(UOH4) {
-	Name(_ADR, 0x00130002)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH4 */
-
-/* 0:16.0 - OHCI */
-Device(UOH5) {
-	Name(_ADR, 0x00160000)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH5 */
-
-/* 0:16.2 - EHCI */
-Device(UOH6) {
-	Name(_ADR, 0x00160002)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UOH5 */
-
-Device(UEH1) {
-	Name(_ADR, 0x00140005)
-	Name(_PRW, Package() {0x0B, 3})
-} /* end UEH1 */
diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h
deleted file mode 100644
index b3fb37dbc8..0000000000
--- a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_PCI_INT_DEFS_H
-#define AMD_PCI_INT_DEFS_H
-
-/*
- * PIRQ and device routing - these define the index
- * into the FCH PCI_INTR 0xC00/0xC01 interrupt
- * routing table
- */
-#define FCH_INT_TABLE_SIZE 0x54
-
-#define PIRQ_NC		0x1F	/* Not Used */
-#define PIRQ_A		0x00	/* INT A */
-#define PIRQ_B		0x01	/* INT B */
-#define PIRQ_C		0x02	/* INT C */
-#define PIRQ_D		0x03	/* INT D */
-#define PIRQ_E		0x04	/* INT E */
-#define PIRQ_F		0x05	/* INT F */
-#define PIRQ_G		0x06	/* INT G */
-#define PIRQ_H		0x07	/* INT H */
-#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings - See FCH Spec */
-#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
-#define PIRQ_MISC1	0x0A	/* Miscellaneous1 IRQ Settings */
-#define PIRQ_MISC2	0x0B	/* Miscellaneous2 IRQ Settings */
-#define PIRQ_SIRQA	0x0C	/* Serial IRQ INTA */
-#define PIRQ_SIRQB	0x0D	/* Serial IRQ INTB */
-#define PIRQ_SIRQC	0x0E	/* Serial IRQ INTC */
-#define PIRQ_SIRQD	0x0F	/* Serial IRQ INTD */
-#define PIRQ_SCI	0x10	/* SCI IRQ */
-#define PIRQ_SMBUS	0x11	/* SMBUS	14h.0 */
-#define PIRQ_ASF	0x12	/* ASF */
-#define PIRQ_HDA	0x13	/* HDA		14h.2 */
-#define PIRQ_FC		0x14	/* FC */
-#define PIRQ_GEC	0x15	/* GEC */
-#define PIRQ_PMON	0x16	/* Performance Monitor */
-#define PIRQ_IMC0	0x20	/* IMC INT0 */
-#define PIRQ_IMC1	0x21	/* IMC INT1 */
-#define PIRQ_IMC2	0x22	/* IMC INT2 */
-#define PIRQ_IMC3	0x23	/* IMC INT3 */
-#define PIRQ_IMC4	0x24	/* IMC INT4 */
-#define PIRQ_IMC5	0x25	/* IMC INT5 */
-#define PIRQ_OHCI1	0x30	/* USB OHCI	12h.0 */
-#define PIRQ_EHCI1	0x31	/* USB EHCI	12h.2 */
-#define PIRQ_OHCI2	0x32	/* USB OHCI	13h.0 */
-#define PIRQ_EHCI2	0x33	/* USB EHCI	13h.2 */
-#define PIRQ_OHCI3	0x34	/* USB OHCI	16h.0 */
-#define PIRQ_EHCI3	0x35	/* USB EHCI	16h.2 */
-#define PIRQ_OHCI4	0x36	/* USB OHCI	14h.5 */
-#define PIRQ_IDE	0x40	/* IDE		14h.1 */
-#define PIRQ_SATA	0x41	/* SATA		11h.0 */
-#define PIRQ_GPP0	0x50	/* GPP INT 0 */
-#define PIRQ_GPP1	0x51	/* GPP INT 1 */
-#define PIRQ_GPP2	0x52	/* GPP INT 2 */
-#define PIRQ_GPP3	0x53	/* GPP INT 3 */
-
-#endif /* AMD_PCI_INT_DEFS_H */
diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h
deleted file mode 100644
index 578c2b7f57..0000000000
--- a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_PCI_INT_TYPES_H
-#define AMD_PCI_INT_TYPES_H
-
-const char *intr_types[] = {
-	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
-	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
-	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t",
-	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
-	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
-	[0x40] = "IDE\t", "SATA\t",
-	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"
-};
-
-#endif /* AMD_PCI_INT_TYPES_H */
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
deleted file mode 100644
index 636e5a8eec..0000000000
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <arch/bootblock.h>
-#include <device/pci_ops.h>
-
-static void enable_rom(void)
-{
-	u16 word;
-	u32 dword;
-	const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
-	/* SB800 LPC Bridge 0:20:3:44h.
-	 * BIT6: Port Enable for serial port 0x3f8-0x3ff
-	 * BIT29: Port Enable for KBC port 0x60 and 0x64
-	 * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
-	 */
-	dword = pci_s_read_config32(dev, 0x44);
-	//dword |= (1<<6) | (1<<29) | (1<<30);
-	/* Turn on all of LPC IO Port decode enable */
-	dword = 0xffffffff;
-	pci_s_write_config32(dev, 0x44, dword);
-
-	/* SB800 LPC Bridge 0:20:3:48h.
-	 * BIT0: Port Enable for SuperIO 0x2E-0x2F
-	 * BIT1: Port Enable for SuperIO 0x4E-0x4F
-	 * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
-	 * BIT6: Port Enable for RTC IO 0x70-0x73
-	 * BIT21: Port Enable for Port 0x80
-	 */
-	dword = pci_s_read_config32(dev, 0x48);
-	dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
-	pci_s_write_config32(dev, 0x48, dword);
-
-	/* Enable ROM access */
-	word = pci_s_read_config16(dev, 0x6c);
-	word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6);
-	pci_s_write_config16(dev, 0x6c, word);
-}
-
-static void enable_prefetch(void)
-{
-	u32 dword;
-	const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
-
-	/* Enable PrefetchEnSPIFromHost */
-	dword = pci_s_read_config32(dev, 0xb8);
-	pci_s_write_config32(dev, 0xb8, dword | (1 << 24));
-}
-
-static void enable_spi_fast_mode(void)
-{
-	u32 dword;
-	const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
-
-	// set temp MMIO base
-	volatile u32 *spi_base = (void *)0xa0000000;
-	u32 save = pci_s_read_config32(dev, 0xa0);
-	pci_s_write_config32(dev, 0xa0, (u32)spi_base | 2);
-
-	// early enable of SPI 33 MHz fast mode read
-	dword = spi_base[3];
-	spi_base[3] = (dword & ~(3 << 14)) | (1 << 14);
-	spi_base[0] = spi_base[0] | (1 << 18);	// fast read enable
-
-	pci_s_write_config32(dev, 0xa0, save);
-}
-
-static void enable_clocks(void)
-{
-	u32 reg32;
-
-	// Program SB800 MiscClkCntrl register to configure clock output on the
-	// 14M_25M_48M_OSC ball usually used for the Super-I/O.
-	// Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz,
-	// which is the SB800's power up default.  We could switch back to 14
-	// in the mainboard's romstage.c, but then the clock frequency would
-	// change twice.
-	reg32 = misc_read32(0x40);
-	reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default)
-#if !CONFIG(SUPERIO_WANTS_14MHZ_CLOCK)
-	reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz
-#endif
-	misc_write32(0x40, reg32);
-}
-
-void bootblock_early_southbridge_init(void)
-{
-	/* Setup the ROM access for 2M */
-	enable_rom();
-	enable_prefetch();
-	enable_spi_fast_mode();
-
-	// Program AcpiMmioEn to enable MMIO access to MiscCntrl register
-	enable_acpimmio_decode_pm24();
-	enable_clocks();
-}
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
deleted file mode 100644
index f1ac4c920c..0000000000
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/hpet.h> /* Include this before OEM.h to have HPET_BASE_ADDRESS from arch/x86 */
-#include "SBPLATFORM.h"
-#include "cfg.h"
-#include <OEM.h>
-
-#include <acpi/acpi.h>
-
-/**
- * @brief South Bridge CIMx configuration
- *
- * should be called before executing CIMx functions.
- * this function will be called in romstage and ramstage.
- */
-void sb800_cimx_config(AMDSBCFG *sb_config)
-{
-	uint16_t bios_size = BIOS_SIZE;
-	if (!sb_config)
-		return;
-
-	sb_config->S3Resume = acpi_is_wakeup_s3();
-
-	/* header */
-	sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS;
-
-	/* static Build Parameters */
-	sb_config->BuildParameters.BiosSize = bios_size;
-	sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
-	sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
-	sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
-	sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
-	sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
-	sb_config->BuildParameters.SioHwmBaseAddress = SIO_HWM_BASE_ADDRESS;
-	sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
-	sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS;
-	sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
-	sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
-	sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
-	sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
-	sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
-	sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
-	sb_config->BuildParameters.OhciSsid = OHCI_SSID;
-	sb_config->BuildParameters.EhciSsid = EHCI_SSID;
-	sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
-	sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
-	sb_config->BuildParameters.IdeSsid = IDE_SSID;
-	sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
-	sb_config->BuildParameters.LpcSsid = LPC_SSID;
-	sb_config->BuildParameters.PCIBSsid = PCIB_SSID;
-	sb_config->BuildParameters.SpreadSpectrumType = Spread_Spectrum_Type;
-	sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
-	sb_config->BuildParameters.ImcEnableOverWrite = IMC_ENABLE_OVER_WRITE;
-
-	/* General */
-	sb_config->SpreadSpectrum = SPREAD_SPECTRUM;
-	sb_config->PciClks = PCI_CLOCK_CTRL;
-	sb_config->HpetTimer = HPET_TIMER;
-	sb_config->SbSpiSpeedSupport = 1;
-
-	/* USB */
-	sb_config->USBMODE.UsbModeReg = USB_CONFIG;
-	sb_config->SbUsbPll = 0;
-	/* CG PLL multiplier for USB Rx 1.1 mode (0=disable, 1=enable) */
-	sb_config->UsbRxMode = USB_RX_MODE;
-
-	/* SATA */
-	sb_config->SataClass = SATA_MODE;
-	sb_config->SataIdeMode = SATA_IDE_MODE;
-	sb_config->SataPortMultCap = SATA_PORT_MULT_CAP_RESERVED;
-	sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
-	sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
-								//TODO: set to secondary not take effect.
-	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE;
-	sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
-
-	/* Azalia HDA */
-	sb_config->AzaliaController = AZALIA_CONTROLLER;
-	sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
-	sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN;
-	/* Mainboard Specific Azalia Codec Verb Table */
-#ifdef AZALIA_OEM_VERB_TABLE
-	sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = (CODECTBLLIST *)AZALIA_OEM_VERB_TABLE;
-#else
-	sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL;
-#endif
-	/* LPC */
-	/* SuperIO hardware monitor register access */
-	sb_config->SioHwmPortEnable = CONFIG(SB_SUPERIO_HWM);
-
-	/*
-	 * GPP. default configure only enable port0 with 4 lanes,
-	 * configure in devicetree.cb would overwrite the default configuration
-	 */
-	sb_config->GppFunctionEnable = GPP_CONTROLLER;
-	sb_config->GppLinkConfig = GPP_CFGMODE;
-	//sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE;
-	sb_config->PORTCONFIG[0].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
-	sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
-	sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
-	sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
-	sb_config->GppUnhidePorts = SB_GPP_UNHIDE_PORTS;
-	sb_config->NbSbGen2 = NB_SB_GEN2;
-	sb_config->GppGen2 = SB_GPP_GEN2;
-
-	//cimx BTS fix
-	sb_config->GppMemWrImprove = TRUE;
-	sb_config->SbPcieOrderRule = TRUE;
-	sb_config->AlinkPhyPllPowerDown = TRUE;
-	sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving
-	sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06
-	sb_config->GecConfig = GEC_CONFIG;
-}
diff --git a/src/southbridge/amd/cimx/sb800/cfg.h b/src/southbridge/amd/cimx/sb800/cfg.h
deleted file mode 100644
index 25b2a45cab..0000000000
--- a/src/southbridge/amd/cimx/sb800/cfg.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SB800_CFG_H_
-#define _SB800_CFG_H_
-
-/**
- * @brief South Bridge CIMx configuration
- *
- */
-void sb800_cimx_config(AMDSBCFG *sb_cfg);
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb800/chip.h b/src/southbridge/amd/cimx/sb800/chip.h
deleted file mode 100644
index 48c9622aef..0000000000
--- a/src/southbridge/amd/cimx/sb800/chip.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _CIMX_SB800_CHIP_H_
-#define _CIMX_SB800_CHIP_H_
-#include "fan.h" /* include for #defines used in devicetree.cb */
-
-/*
- * configuration set in mainboard/devicetree.cb
- *  boot_switch_sata_ide:
- *   0 -set SATA as primary, PATA(IDE) as secondary.
- *   1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
- *  gpp_configuration - The configuration of General Purpose Port A/B/C/D
- *   0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
- *   2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
- *   3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
- *   4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
- */
-struct southbridge_amd_cimx_sb800_config
-{
-	u32 boot_switch_sata_ide : 1;
-	u32 disconnect_pcib : 1;
-	u8  gpp_configuration;
-
-	/*
-	 * SB800 IMC and fan control
-	 */
-
-	u16 imc_port_address;
-
-	u32 fan0_enabled : 1;
-	u32 fan1_enabled : 1;
-	u32 fan2_enabled : 1;
-	u32 fan3_enabled : 1;
-	u32 fan4_enabled : 1;
-	u32 imc_fan_zone0_enabled : 1;
-	u32 imc_fan_zone1_enabled : 1;
-	u32 imc_fan_zone2_enabled : 1;
-	u32 imc_fan_zone3_enabled : 1;
-	u32 imc_tempin0_enabled : 1;
-	u32 imc_tempin1_enabled : 1;
-	u32 imc_tempin2_enabled : 1;
-	u32 imc_tempin3_enabled : 1;
-
-	union {
-		struct {
-			u8  fan0_control_reg_value;
-			u8  fan0_frequency_reg_value;
-			u8  fan0_low_duty_reg_value;
-			u8  fan0_med_duty_reg_value;
-			u8  fan0_multiplier_reg_value;
-			u8  fan0_low_temp_lo_reg_value;
-			u8  fan0_low_temp_hi_reg_value;
-			u8  fan0_med_temp_lo_reg_value;
-			u8  fan0_med_temp_hi_reg_value;
-			u8  fan0_high_temp_lo_reg_value;
-			u8  fan0_high_temp_hi_reg_value;
-			u8  fan0_linear_range_reg_value;
-			u8  fan0_linear_hold_reg_value;
-		};
-		u8  fan0_config_vals[FAN_REGISTER_COUNT];
-	};
-
-	union {
-		struct {
-			u8  fan1_control_reg_value;
-			u8  fan1_frequency_reg_value;
-			u8  fan1_low_duty_reg_value;
-			u8  fan1_med_duty_reg_value;
-			u8  fan1_multiplier_reg_value;
-			u8  fan1_low_temp_lo_reg_value;
-			u8  fan1_low_temp_hi_reg_value;
-			u8  fan1_med_temp_lo_reg_value;
-			u8  fan1_med_temp_hi_reg_value;
-			u8  fan1_high_temp_lo_reg_value;
-			u8  fan1_high_temp_hi_reg_value;
-			u8  fan1_linear_range_reg_value;
-			u8  fan1_linear_hold_reg_value;
-		};
-		u8  fan1_config_vals[FAN_REGISTER_COUNT];
-	};
-
-	union {
-		struct {
-			u8  fan2_control_reg_value;
-			u8  fan2_frequency_reg_value;
-			u8  fan2_low_duty_reg_value;
-			u8  fan2_med_duty_reg_value;
-			u8  fan2_multiplier_reg_value;
-			u8  fan2_low_temp_lo_reg_value;
-			u8  fan2_low_temp_hi_reg_value;
-			u8  fan2_med_temp_lo_reg_value;
-			u8  fan2_med_temp_hi_reg_value;
-			u8  fan2_high_temp_lo_reg_value;
-			u8  fan2_high_temp_hi_reg_value;
-			u8  fan2_linear_range_reg_value;
-			u8  fan2_linear_hold_reg_value;
-		};
-		u8  fan2_config_vals[FAN_REGISTER_COUNT];
-	};
-
-	union {
-		struct {
-			u8  fan3_control_reg_value;
-			u8  fan3_frequency_reg_value;
-			u8  fan3_low_duty_reg_value;
-			u8  fan3_med_duty_reg_value;
-			u8  fan3_multiplier_reg_value;
-			u8  fan3_low_temp_lo_reg_value;
-			u8  fan3_low_temp_hi_reg_value;
-			u8  fan3_med_temp_lo_reg_value;
-			u8  fan3_med_temp_hi_reg_value;
-			u8  fan3_high_temp_lo_reg_value;
-			u8  fan3_high_temp_hi_reg_value;
-			u8  fan3_linear_range_reg_value;
-			u8  fan3_linear_hold_reg_value;
-		};
-		u8  fan3_config_vals[FAN_REGISTER_COUNT];
-	};
-
-	union {
-		struct {
-			u8  fan4_control_reg_value;
-			u8  fan4_frequency_reg_value;
-			u8  fan4_low_duty_reg_value;
-			u8  fan4_med_duty_reg_value;
-			u8  fan4_multiplier_reg_value;
-			u8  fan4_low_temp_lo_reg_value;
-			u8  fan4_low_temp_hi_reg_value;
-			u8  fan4_med_temp_lo_reg_value;
-			u8  fan4_med_temp_hi_reg_value;
-			u8  fan4_high_temp_lo_reg_value;
-			u8  fan4_high_temp_hi_reg_value;
-			u8  fan4_linear_range_reg_value;
-			u8  fan4_linear_hold_reg_value;
-		};
-		u8  fan4_config_vals[FAN_REGISTER_COUNT];
-	};
-
-	union {
-		struct {
-			u8 imc_zone0_mode1;
-			u8 imc_zone0_mode2;
-			u8 imc_zone0_temp_offset;
-			u8 imc_zone0_hysteresis;
-			u8 imc_zone0_smbus_addr;
-			u8 imc_zone0_smbus_num;
-			u8 imc_zone0_pwm_step;
-			u8 imc_zone0_ramping;
-		};
-		u8  imc_zone0_config_vals[IMC_FAN_CONFIG_COUNT];
-	};
-	u8  imc_zone0_thresholds[IMC_FAN_THRESHOLD_COUNT];
-	u8  imc_zone0_fanspeeds[IMC_FAN_SPEED_COUNT];
-
-	union {
-		struct {
-		u8  imc_zone1_mode1;
-		u8  imc_zone1_mode2;
-		u8  imc_zone1_temp_offset;
-		u8  imc_zone1_hysteresis;
-		u8  imc_zone1_smbus_addr;
-		u8  imc_zone1_smbus_num;
-		u8  imc_zone1_pwm_step;
-		u8  imc_zone1_ramping;
-		};
-		u8  imc_zone1_config_vals[IMC_FAN_CONFIG_COUNT];
-	};
-	u8  imc_zone1_thresholds[IMC_FAN_THRESHOLD_COUNT];
-	u8  imc_zone1_fanspeeds[IMC_FAN_SPEED_COUNT];
-
-	union {
-		struct {
-			u8  imc_zone2_mode1;
-			u8  imc_zone2_mode2;
-			u8  imc_zone2_temp_offset;
-			u8  imc_zone2_hysteresis;
-			u8  imc_zone2_smbus_addr;
-			u8  imc_zone2_smbus_num;
-			u8  imc_zone2_pwm_step;
-			u8  imc_zone2_ramping;
-		};
-		u8  imc_zone2_config_vals[IMC_FAN_CONFIG_COUNT];
-	};
-	u8  imc_zone2_thresholds[IMC_FAN_THRESHOLD_COUNT];
-	u8  imc_zone2_fanspeeds[IMC_FAN_SPEED_COUNT];
-
-	union {
-		struct {
-			u8  imc_zone3_mode1;
-			u8  imc_zone3_mode2;
-			u8  imc_zone3_temp_offset;
-			u8  imc_zone3_hysteresis;
-			u8  imc_zone3_smbus_addr;
-			u8  imc_zone3_smbus_num;
-			u8  imc_zone3_pwm_step;
-			u8  imc_zone3_ramping;
-		};
-		u8 imc_zone3_config_vals[IMC_FAN_CONFIG_COUNT];
-	};
-	u8  imc_zone3_thresholds[IMC_FAN_THRESHOLD_COUNT];
-	u8  imc_zone3_fanspeeds[IMC_FAN_SPEED_COUNT];
-
-	u32 imc_tempin0_at;
-	u32 imc_tempin0_ct;
-	u8 imc_tempin0_tuning_param;
-
-	u32 imc_tempin1_at;
-	u32 imc_tempin1_ct;
-	u8  imc_tempin1_tuning_param;
-
-	u32 imc_tempin2_at;
-	u32 imc_tempin2_ct;
-	u8  imc_tempin2_tuning_param;
-
-	u32 imc_tempin3_at;
-	u32 imc_tempin3_ct;
-	u8  imc_tempin3_tuning_param;
-
-};
-#endif /* _CIMX_SB800_CHIP_H_ */
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
deleted file mode 100644
index 7ea179c94e..0000000000
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include "SBPLATFORM.h"
-#include "sb_cimx.h"
-#include "cfg.h"		/*sb800_cimx_config*/
-
-/**
- * @brief South Bridge CIMx romstage entry,
- *        wrapper of sbPowerOnInit entry point.
- */
-void sb_Poweron_Init(void)
-{
-	AMDSBCFG sb_early_cfg;
-
-	sb800_cimx_config(&sb_early_cfg);
-	//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
-	//AmdSbDispatcher(&sb_early_cfg);
-	//TODO
-	//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
-	// VerifyImage() will fail, LocateImage() takes minutes to find the image.
-	sbPowerOnInit(&sb_early_cfg);
-}
-
-/**
- * CIMX not set the clock to 48Mhz until sbBeforePciInit,
- * coreboot may need to set this even more earlier
- */
-void sb800_clk_output_48Mhz(void)
-{
-
-	misc_write32(0x40, misc_read32(0x40) & (~5));
-	misc_write32(0x40, misc_read32(0x40) | 2);
-}
diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c
deleted file mode 100644
index b4ea285ed7..0000000000
--- a/src/southbridge/amd/cimx/sb800/fadt.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <console/console.h>
-#include <acpi/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <version.h>
-
-#include "SBPLATFORM.h"
-
-#ifndef FADT_BOOT_ARCH
-#if LEGACY_FREE
-	#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
-#else
-	#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
-#endif
-#endif
-
-/*
- * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
- * in the ACPI 3.0b specification.
- */
-void acpi_fill_fadt(acpi_fadt_t *fadt)
-{
-	u16 val = 0;
-
-	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
-
-	fadt->sci_int = 9;		/* HUDSON 1 - IRQ 09 - ACPI SCI */
-
-	val = PM1_EVT_BLK_ADDRESS;
-	WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
-	val = PM1_CNT_BLK_ADDRESS;
-	WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
-	val = PM1_TMR_BLK_ADDRESS;
-	WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
-	val = GPE0_BLK_ADDRESS;
-	WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
-
-	/* CpuControl is in \_PR.CP00, 6 bytes */
-	val = CPU_CNT_BLK_ADDRESS;
-	WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
-	val = 0;
-	WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
-	val = ACPI_PMA_CNT_BLK_ADDRESS;
-	WritePMIO(SB_PMIOA_REG6E, AccWidthUint16, &val);
-
-	/* AcpiDecodeEnable, When set, SB uses the contents of the
-	 * PM registers at index 60-6B to decode ACPI I/O address.
-	 * AcpiSmiEn & SmiCmdEn*/
-	val = BIT0 | BIT1 | BIT2 | BIT4;
-	WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
-
-	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
-	outl(0x1, PM1_CNT_BLK_ADDRESS);		  /* set SCI_EN */
-	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
-	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
-	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
-	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
-
-	fadt->pm1_evt_len = 4;	/* 32 bits */
-	fadt->pm1_cnt_len = 2;	/* 16 bits */
-	fadt->pm2_cnt_len = 1;	/* 8 bits */
-	fadt->pm_tmr_len = 4;	/* 32 bits */
-	fadt->gpe0_blk_len = 8;	/* 64 bits */
-
-	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
-	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
-	fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */
-	fadt->duty_width = 3;	/* CLK_VAL bits 3:1 */
-	fadt->day_alrm = 0;	/* 0x7d these have to be */
-	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->iapc_boot_arch = FADT_BOOT_ARCH;	/* See table 5-10 */
-	fadt->res2 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
-	fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
-				ACPI_FADT_C1_SUPPORTED |
-				ACPI_FADT_SLEEP_BUTTON |
-				ACPI_FADT_S4_RTC_WAKE |
-				ACPI_FADT_32BIT_TIMER |
-				ACPI_FADT_PCI_EXPRESS_WAKE |
-				ACPI_FADT_S4_RTC_VALID |
-				ACPI_FADT_REMOTE_POWER_ON;
-
-	fadt->ARM_boot_arch = 0;	/* Must be zero if ACPI Revision <= 5.0 */
-
-	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
-	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED;
-	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
-	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
-	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; /* EventStatus + Event Enable */
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
-	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
-	fadt->x_gpe0_blk.addrh = 0x0;
-}
diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c
deleted file mode 100644
index f5e0a48f4d..0000000000
--- a/src/southbridge/amd/cimx/sb800/fan.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/device.h>
-#include <device/pci.h>		/* device_operations */
-#include <device/pci_ops.h>
-#include "SBPLATFORM.h"
-#include "sb_cimx.h"
-#include "chip.h"		/* struct southbridge_amd_cimx_sb800_config */
-#include "fan.h"
-
-void init_sb800_MANUAL_fans(struct device *dev)
-{
-	int i;
-	struct southbridge_amd_cimx_sb800_config *sb_chip =
-		(struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
-
-	/* Init Fan 0 */
-	if (sb_chip->fan0_enabled)
-		for (i = 0; i < FAN_REGISTER_COUNT; i++)
-			pm2_write8(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]);
-
-	/* Init Fan 1 */
-	if (sb_chip->fan1_enabled)
-		for (i = 0; i < FAN_REGISTER_COUNT; i++)
-			pm2_write8(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]);
-
-	/* Init Fan 2 */
-	if (sb_chip->fan2_enabled)
-		for (i = 0; i < FAN_REGISTER_COUNT; i++)
-			pm2_write8(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]);
-
-	/* Init Fan 3 */
-	if (sb_chip->fan3_enabled)
-		for (i = 0; i < FAN_REGISTER_COUNT; i++)
-			pm2_write8(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]);
-
-	/* Init Fan 4 */
-	if (sb_chip->fan4_enabled)
-		for (i = 0; i < FAN_REGISTER_COUNT; i++)
-			pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]);
-}
-
-void init_sb800_IMC_fans(struct device *dev)
-{
-	AMDSBCFG sb_config;
-	unsigned char *message_ptr;
-	int i;
-	struct southbridge_amd_cimx_sb800_config *sb_chip =
-		(struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
-
-	/*
-	 * The default I/O address of the IMC configuration register index
-	 *  port is 0x6E. Change the IMC Config port I/O Address if it
-	 *  conflicts with other components in the system.
-	 *
-	 * Device 20, Function 3, Reg 0xA4
-	 * [0]: if 1, the address specified in IMC_PortAddress is used.
-	 * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E)
-	 */
-
-	pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01);
-
-	/*
-	 * Do an initial manual setup of the fans for things like polarity
-	 * and frequency.
-	 */
-	init_sb800_MANUAL_fans(dev);
-
-	/*
-	 * FLAG for Func 81/83/85/89 support (1=On,0=Off)
-	 * Bit0-3   = Func 81 Zone0-Zone3
-	 * Bit4-7   = Func 83 Zone0-Zone3
-	 * Bit8-11  = Func 85 Zone0-Zone3
-	 * Bit12-15 = Func 89 Tempin Channel0-Channel3
-	 */
-	sb_config.Pecstruct.IMCFUNSupportBitMap = 0;
-
-/*
- ********** Zone 0 **********
- */
-if (sb_chip->imc_fan_zone0_enabled) {
-
-	sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE0;
-
-	/* EC LDN9 function 81 zone 0 */
-	sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0;
-	message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2;
-	for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone0_config_vals[i];
-
-	/* EC LDN9 function 83 zone 0 - Temperature Thresholds */
-	sb_config.Pecstruct.MSGFun83zone0MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0;
-	sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00;
-	message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2;
-	for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone0_thresholds[i];
-
-	/*EC LDN9 function 85 zone 0 - Fan Speeds */
-	sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0;
-	message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2;
-	for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i];
-}
-
-/*
- ********** Zone 1 **********
- */
-if (sb_chip->imc_fan_zone1_enabled) {
-
-	sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE1;
-
-	/* EC LDN9 function 81 zone 1 */
-	sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1;
-	message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2;
-	for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone1_config_vals[i];
-
-	/* EC LDN9 function 83 zone 1 - Temperature Thresholds */
-	sb_config.Pecstruct.MSGFun83zone1MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1;
-	sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00;
-	message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2;
-	for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone1_thresholds[i];
-
-	/* EC LDN9 function 85 zone 1 - Fan Speeds */
-	sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1;
-	message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2;
-	for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i];
-}
-
-/*
- ********** Zone 2 **********
- */
-if (sb_chip->imc_fan_zone2_enabled) {
-
-	sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE2;
-
-	/* EC LDN9 function 81 zone 2 */
-	sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2;
-	message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2;
-	for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone2_config_vals[i];
-
-	/* EC LDN9 function 83 zone 2 */
-	sb_config.Pecstruct.MSGFun83zone2MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2;
-	sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00;
-	message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2;
-	for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone2_thresholds[i];
-
-	/* EC LDN9 function 85 zone 2 */
-	sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2;
-	message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2;
-	for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i];
-}
-
-/*
- ********** Zone 3 **********
- */
-
-if (sb_chip->imc_fan_zone3_enabled) {
-
-	sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE3;
-
-	/* EC LDN9 function 81 zone 3 */
-	sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3;
-	message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2;
-	for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone3_config_vals[i];
-
-	/* EC LDN9 function 83 zone 3 */
-	sb_config.Pecstruct.MSGFun83zone3MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3;
-	sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00;
-	message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2;
-	for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone3_thresholds[i];
-
-	/* EC LDN9 function 85 zone 3 */
-	sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3;
-	message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2;
-	for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
-		*(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i];
-}
-
-	/*
-	 * EC LDN9 function 89 - Set HWM TEMPIN Temperature Calculation Parameters
-	 * This function provides the critical parameters of the HWM TempIn
-	 * sensors, IMC would not perform temperature measurement using those
-	 * sensors until the parameters are provided.
-	 */
-
-if (sb_chip->imc_tempin0_enabled) {
-
-	sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN0;
-
-	/* EC LDN9 function 89 TEMPIN channel 0 */
-	sb_config.Pecstruct.MSGFun89zone0MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun89zone0MSGREG1 = 0x00;
-	sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff);
-	sb_config.Pecstruct.MSGFun89zone0MSGREG3 = ((sb_chip->imc_tempin0_at >> 8)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone0MSGREG4 = ((sb_chip->imc_tempin0_at >> 16) & 0xff);
-	sb_config.Pecstruct.MSGFun89zone0MSGREG5 = ((sb_chip->imc_tempin0_at >> 24) & 0xff);
-	sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff);
-	sb_config.Pecstruct.MSGFun89zone0MSGREG7 = ((sb_chip->imc_tempin0_ct >> 8)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone0MSGREG8 = ((sb_chip->imc_tempin0_ct >> 16)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone0MSGREG9 = ((sb_chip->imc_tempin0_ct >> 24)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone0MSGREGA = sb_chip->imc_tempin0_tuning_param;
-}
-
-if (sb_chip->imc_tempin1_enabled) {
-
-	sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN1;
-
-	/* EC LDN9 function 89 TEMPIN channel 1 */
-	sb_config.Pecstruct.MSGFun89zone1MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun89zone1MSGREG1 = 0x01;
-	sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff);
-	sb_config.Pecstruct.MSGFun89zone1MSGREG3 = ((sb_chip->imc_tempin1_at >> 8)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone1MSGREG4 = ((sb_chip->imc_tempin1_at >> 16) & 0xff);
-	sb_config.Pecstruct.MSGFun89zone1MSGREG5 = ((sb_chip->imc_tempin1_at >> 24) & 0xff);
-	sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff);
-	sb_config.Pecstruct.MSGFun89zone1MSGREG7 = ((sb_chip->imc_tempin1_ct >> 8)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone1MSGREG8 = ((sb_chip->imc_tempin1_ct >> 16)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone1MSGREG9 = ((sb_chip->imc_tempin1_ct >> 24)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone1MSGREGA = sb_chip->imc_tempin1_tuning_param;
-}
-
-if (sb_chip->imc_tempin2_enabled) {
-
-	sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN2;
-
-	/* EC LDN9 function 89 TEMPIN channel 2 */
-	sb_config.Pecstruct.MSGFun89zone2MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun89zone2MSGREG1 = 0x02;
-	sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff);
-	sb_config.Pecstruct.MSGFun89zone2MSGREG3 = ((sb_chip->imc_tempin2_at >> 8)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone2MSGREG4 = ((sb_chip->imc_tempin2_at >> 16) & 0xff);
-	sb_config.Pecstruct.MSGFun89zone2MSGREG5 = ((sb_chip->imc_tempin2_at >> 24) & 0xff);
-	sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff);
-	sb_config.Pecstruct.MSGFun89zone2MSGREG7 = ((sb_chip->imc_tempin2_ct >> 8)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone2MSGREG8 = ((sb_chip->imc_tempin2_ct >> 16)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone2MSGREG9 = ((sb_chip->imc_tempin2_ct >> 24)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone2MSGREGA = sb_chip->imc_tempin2_tuning_param;
-}
-
-if (sb_chip->imc_tempin3_enabled) {
-
-	sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN3;
-
-	/* EC LDN9 function 89 TEMPIN channel 3 */
-	sb_config.Pecstruct.MSGFun89zone3MSGREG0 = 0x00;
-	sb_config.Pecstruct.MSGFun89zone3MSGREG1 = 0x03;
-	sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff);
-	sb_config.Pecstruct.MSGFun89zone3MSGREG3 = ((sb_chip->imc_tempin3_at >> 8)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone3MSGREG4 = ((sb_chip->imc_tempin3_at >> 16) & 0xff);
-	sb_config.Pecstruct.MSGFun89zone3MSGREG5 = ((sb_chip->imc_tempin3_at >> 24) & 0xff);
-	sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff);
-	sb_config.Pecstruct.MSGFun89zone3MSGREG7 = ((sb_chip->imc_tempin3_ct >> 8)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone3MSGREG8 = ((sb_chip->imc_tempin3_ct >> 16)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone3MSGREG9 = ((sb_chip->imc_tempin3_ct >> 24)  & 0xff);
-	sb_config.Pecstruct.MSGFun89zone3MSGREGA = sb_chip->imc_tempin3_tuning_param;
-}
-
-	/* Set up the sb_config structure for the fan control initialization */
-	sb_config.StdHeader.Func = SB_EC_FANCONTROL;
-
-	AmdSbDispatcher(&sb_config);
-}
diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h
deleted file mode 100644
index 9b763a5877..0000000000
--- a/src/southbridge/amd/cimx/sb800/fan.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SB800_FAN_H_
-#define _SB800_FAN_H_
-
-#include <device/device.h>
-
-void init_sb800_IMC_fans(struct device *dev);
-void init_sb800_MANUAL_fans(struct device *dev);
-
-/* Fan Register Definitions */
-#define FAN_0_OFFSET				0x00
-#define FAN_1_OFFSET				0x10
-#define FAN_2_OFFSET				0x20
-#define FAN_3_OFFSET				0x30
-#define FAN_4_OFFSET				0x40
-
-#define FAN_INPUT_CONTROL_REG		0x00
-#define FAN_CONTROL_REG				0x01
-#define FAN_FREQUENCY_REG			0x02
-#define FAN_LOW_DUTY_REG			0x03
-#define FAN_MED_DUTY_REG			0x04
-#define FAN_MULTIPLIER_REG			0x05
-#define FAN_LOW_TEMP_LO_REG			0x06
-#define FAN_LOW_TEMP_HI_REG			0x07
-#define FAN_MED_TEMP_LO_REG			0x08
-#define FAN_MED_TEMP_HI_REG			0x09
-#define FAN_HIGH_TEMP_LO_REG		0x0A
-#define FAN_HIGH_TEMP_HI_REG		0x0B
-#define FAN_LINEAR_RANGE_REG		0x0C
-#define FAN_LINEAR_HOLD_REG			0x0D
-
-/* FanXInputControl Definitions */
-#define FAN_INPUT_INTERNAL_DIODE	0
-#define FAN_INPUT_TEMP0				1
-#define FAN_INPUT_TEMP1				2
-#define FAN_INPUT_TEMP2				3
-#define FAN_INPUT_TEMP3				4
-#define FAN_INPUT_TEMP0_FILTER		5
-#define FAN_INPUT_ZERO				6
-#define FAN_INPUT_DISABLED			7
-
-/* FanXControl Definitions */
-#define FAN_AUTOMODE				(1 << 0)
-#define FAN_LINEARMODE				(1 << 1)
-#define FAN_STEPMODE				0 /* ~(1 << 1) */
-#define FAN_POLARITY_HIGH			(1 << 2)
-#define FAN_POLARITY_LOW			0 /*~(1 << 2) */
-
-/* FanXLowDuty Definitions */
-#define FAN_POLARITY_HIGH_MAX_SPEED	0xff
-#define FAN_POLARITY_LOW_MAX_SPEED	0x00
-
-/* FanXFreq Definitions */
-/* Typically, fans run at 25KHz */
-#define FREQ_28KHZ			0x0
-#define FREQ_25KHZ			0x1
-#define FREQ_23KHZ			0x2
-#define FREQ_21KHZ			0x3
-#define FREQ_29KHZ			0x4
-#define FREQ_18KHZ			0x5
-/* Any value > 05h and < F7: Freq = 1/(FreqDiv * 2048 * 15ns) */
-#define FREQ_100HZ			0xF7
-#define FREQ_87HZ			0xF8
-#define FREQ_58HZ			0xF9
-#define FREQ_44HZ			0xFA
-#define FREQ_35HZ			0xFB
-#define FREQ_29HZ			0xFC
-#define FREQ_22HZ			0xFD
-#define FREQ_14HZ			0xFE
-#define FREQ_11HZ			0xFF
-
-/* IMC Fan Control Definitions */
-#define IMC_MODE1_FAN_ENABLED					(1 << 0)
-#define IMC_MODE1_FAN_IMC_CONTROLLED			(1 << 2)
-#define IMC_MODE1_FAN_LINEAR_MODE				(1 << 4)
-#define IMC_MODE1_FAN_STEP_MODE					0 /* ~( 1 << 4 ) */
-#define IMC_MODE1_NO_FANOUT						0 /* ~( 7 << 5 ) */
-#define IMC_MODE1_FANOUT0						(1 << 5)
-#define IMC_MODE1_FANOUT1						(2 << 5)
-#define IMC_MODE1_FANOUT2						(3 << 5)
-#define IMC_MODE1_FANOUT3						(4 << 5)
-#define IMC_MODE1_FANOUT4						(5 << 5)
-
-#define IMC_MODE2_TEMPIN_NONE					0 /* ~( 7 << 0) */
-#define IMC_MODE2_TEMPIN_0						1
-#define IMC_MODE2_TEMPIN_1						2
-#define IMC_MODE2_TEMPIN_2						3
-#define IMC_MODE2_TEMPIN_3						4
-#define IMC_MODE2_INT_TEMPIN					5
-#define IMC_MODE2_TEMPIN_SB_TSI					6
-#define IMC_MODE2_TEMPIN_OTHER					7
-#define IMC_MODE2_FANIN_NONE					0 /* ~ (7 << 3) */
-#define IMC_MODE2_FANIN0						(1 << 3)
-#define IMC_MODE2_FANIN1						(2 << 3)
-#define IMC_MODE2_FANIN2						(3 << 3)
-#define IMC_MODE2_FANIN3						(4 << 3)
-#define IMC_MODE2_FANIN4						(5 << 3)
-#define IMC_MODE2_TEMP_AVERAGING_ENABLED		(1 << 6)
-#define IMC_MODE2_TEMP_AVERAGING_DISABLED		0 /* ~( 1 << 6 ) */
-
-#define IMC_TEMP_SENSOR_ON_SMBUS_0				0
-#define IMC_TEMP_SENSOR_ON_SMBUS_2				1
-#define IMC_TEMP_SENSOR_ON_SMBUS_3				2
-#define IMC_TEMP_SENSOR_ON_SMBUS_4				3
-
-#define IMC_ZONE0								0
-#define IMC_ZONE1								1
-#define IMC_ZONE2								2
-#define IMC_ZONE3								3
-#define IMC_ZONE4								4
-
-#define IMC_TEMPIN_TUNING_DEFAULT_MODE			0
-#define IMC_TEMPIN_TUNING_HIGH_CURRENT_RATIO	1
-#define IMC_TEMPIN_TUNING_HIGH_CURRENT			2
-#define IMC_TEMPIN_TUNING_DISABLE_FILTERING		(1 << 2)
-
-/* IMCFUNSupportBitMap - Zone enable values */
-#define IMC_ENABLE_ZONE0						0x111
-#define IMC_ENABLE_ZONE1						0x222
-#define IMC_ENABLE_ZONE2						0x333
-#define IMC_ENABLE_ZONE3						0x444
-#define IMC_ENABLE_TEMPIN0						(1 << 12)
-#define IMC_ENABLE_TEMPIN1						(1 << 13)
-#define IMC_ENABLE_TEMPIN2						(1 << 14)
-#define IMC_ENABLE_TEMPIN3						(1 << 15)
-
-/* Array size settings */
-#define IMC_FAN_THRESHOLD_COUNT					9
-#define IMC_FAN_SPEED_COUNT						8
-#define IMC_FAN_CONFIG_COUNT					8
-#define FAN_REGISTER_COUNT						15
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb800/gpio_oem.h b/src/southbridge/amd/cimx/sb800/gpio_oem.h
deleted file mode 100644
index f61db5a6bf..0000000000
--- a/src/southbridge/amd/cimx/sb800/gpio_oem.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _CIMX_SB_GPIO_OEM_H_
-#define _CIMX_SB_GPIO_OEM_H_
-
-#define SB_GPIO_REG02   2
-#define SB_GPIO_REG09   9
-#define SB_GPIO_REG10   10
-#define SB_GPIO_REG15   15
-#define SB_GPIO_REG17   17
-#define SB_GPIO_REG21   21
-#define SB_GPIO_REG25   25
-#define SB_GPIO_REG28   28
-
-/* FCH GPIO access helpers */
-#define FCH_IOMUX(gpio_nr) (*(u8 *)((uintptr_t)ACPI_MMIO_BASE + IOMUX_BASE + (gpio_nr)))
-#define FCH_PMIO(reg_nr) (*(u8 *)((uintptr_t)ACPI_MMIO_BASE + PMIO_BASE + (reg_nr)))
-#define FCH_GPIO(gpio_nr) (*(volatile u8 *)((uintptr_t)ACPI_MMIO_BASE + GPIO_BASE + (gpio_nr)))
-
-static inline u8 fch_gpio_state(unsigned int gpio_nr)
-{
-	return FCH_GPIO(gpio_nr) >> 7;
-}
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
deleted file mode 100644
index 88e426a1c5..0000000000
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ /dev/null
@@ -1,439 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/mmio.h>
-#include <device/device.h>
-#include <device/pci.h>		/* device_operations */
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <bootstate.h>
-#include <arch/ioapic.h>
-#include <device/smbus.h>	/* smbus_bus_operations */
-#include <pc80/mc146818rtc.h>
-#include <pc80/i8254.h>
-#include <pc80/i8259.h>
-#include <console/console.h>	/* printk */
-#include <acpi/acpi.h>
-#include <device/pci_ehci.h>
-#include "lpc.h"		/* lpc_read_resources */
-#include "SBPLATFORM.h"		/* Platform Specific Definitions */
-#include "cfg.h"		/* sb800 Cimx configuration */
-#include "chip.h"		/* struct southbridge_amd_cimx_sb800_config */
-#include "sb_cimx.h"		/* AMD CIMX wrapper entries */
-#include "smbus.h"
-#include "fan.h"
-#include "pci_devs.h"
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config
-static AMDSBCFG *sb_config = &sb_late_cfg;
-
-/**
- * @brief Entry point of Southbridge CIMx callout
- *
- * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
- *
- * @param[in] func      Southbridge CIMx Function ID.
- * @param[in] data      Southbridge Input Data.
- * @param[in] config    Southbridge configuration structure pointer.
- *
- */
-static u32 sb800_callout_entry(u32 func, u32 data, void *config)
-{
-	u32 ret = 0;
-	printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
-	switch (func) {
-	case CB_SBGPP_RESET_ASSERT:
-		break;
-
-	case CB_SBGPP_RESET_DEASSERT:
-		break;
-
-	case IMC_FIRMWARE_FAIL:
-		break;
-
-	default:
-		break;
-	}
-
-	printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__);
-	return ret;
-}
-
-#define HOST_CAP                  0x00 /* host capabilities */
-#define HOST_CTL                  0x04 /* global host control */
-#define HOST_IRQ_STAT             0x08 /* interrupt status */
-#define HOST_PORTS_IMPL           0x0c /* bitmap of implemented ports */
-
-#define HOST_CTL_AHCI_EN          (1 << 31) /* AHCI enabled */
-static void ahci_raid_init(struct device *dev)
-{
-	u8 irq = 0;
-	void *bar5;
-	u32 caps, ports, val;
-
-	val = pci_read_config16(dev, PCI_CLASS_DEVICE);
-	if (val == PCI_CLASS_STORAGE_SATA) {
-		printk(BIOS_DEBUG, "AHCI controller ");
-	} else if (val == PCI_CLASS_STORAGE_RAID) {
-		printk(BIOS_DEBUG, "RAID controller ");
-	} else {
-		printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val);
-		return;
-	}
-
-	irq = pci_read_config8(dev, PCI_INTERRUPT_LINE);
-	bar5 = (void *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-	printk(BIOS_DEBUG, "IOMEM base: %p, IRQ: 0x%X\n", bar5, irq);
-
-	caps = read32(bar5 + HOST_CAP);
-	caps = (caps & 0x1F) + 1;
-	ports = read32(bar5 + HOST_PORTS_IMPL);
-	printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports);
-
-	/* make sure ahci is enabled */
-	val = read32(bar5 + HOST_CTL);
-	if (!(val & HOST_CTL_AHCI_EN)) {
-		write32(bar5 + HOST_CTL, val | HOST_CTL_AHCI_EN);
-	}
-
-	dev->command |= PCI_COMMAND_MASTER;
-	pci_write_config8(dev, PCI_COMMAND, dev->command);
-	printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n");
-}
-
-static void lpc_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
-
-	cmos_check_update_date();
-
-	/* Initialize the real time clock.
-	 * The 0 argument tells cmos_init not to
-	 * update CMOS unless it is invalid.
-	 * 1 tells cmos_init to always initialize the CMOS.
-	 */
-	cmos_init(0);
-
-	setup_i8259(); /* Initialize i8259 pic */
-	setup_i8254(); /* Initialize i8254 timers */
-
-	printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__);
-}
-
-static const char *lpc_acpi_name(const struct device *dev)
-{
-	if (dev->path.type != DEVICE_PATH_PCI)
-		return NULL;
-
-	switch (dev->path.pci.devfn) {
-	/* DSDT: acpi/lpc.asl */
-	case LPC_DEVFN:
-		return "LIBR";
-	}
-
-	return NULL;
-}
-
-static struct device_operations lpc_ops = {
-	.read_resources = lpc_read_resources,
-	.set_resources = lpc_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-#if CONFIG(HAVE_ACPI_TABLES)
-	.write_acpi_tables = acpi_write_hpet,
-#endif
-	.init = lpc_init,
-	.scan_bus = scan_static_bus,
-	.ops_pci = &pci_dev_ops_pci,
-	.acpi_name = lpc_acpi_name,
-};
-
-static const struct pci_driver lpc_driver __pci_driver = {
-	.ops = &lpc_ops,
-	.vendor = PCI_VID_ATI,
-	.device = PCI_DID_ATI_SB800_LPC,
-};
-
-static struct device_operations sata_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = ahci_raid_init,
-	.ops_pci = &pci_dev_ops_pci,
-};
-
-static const struct pci_driver ahci_driver __pci_driver = {
-	.ops = &sata_ops,
-	.vendor = PCI_VID_ATI,
-	.device = PCI_DID_ATI_SB800_SATA_AHCI,
-};
-
-static const struct pci_driver raid_driver __pci_driver = {
-	.ops = &sata_ops,
-	.vendor = PCI_VID_ATI,
-	.device = PCI_DID_ATI_SB800_SATA_RAID,
-};
-static const struct pci_driver raid5_driver __pci_driver = {
-	.ops = &sata_ops,
-	.vendor = PCI_VID_ATI,
-	.device = PCI_DID_ATI_SB800_SATA_RAID5,
-};
-
-static struct device_operations usb_ops = {
-	.read_resources = pci_ehci_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.ops_pci = &pci_dev_ops_pci,
-};
-
-/*
- * The pci id of USB ctrl 0 and 1 are the same.
- */
-static const struct pci_driver usb_ohci123_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VID_ATI,
-	.device = PCI_DID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
-};
-
-static const struct pci_driver usb_ehci123_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VID_ATI,
-	.device = PCI_DID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
-};
-
-static const struct pci_driver usb_ohci4_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VID_ATI,
-	.device = PCI_DID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
-};
-
-static struct device_operations azalia_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.ops_pci = &pci_dev_ops_pci,
-};
-
-static const struct pci_driver azalia_driver __pci_driver = {
-	.ops = &azalia_ops,
-	.vendor = PCI_VID_ATI,
-	.device = PCI_DID_ATI_SB800_HDA,
-};
-
-static struct device_operations gec_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.ops_pci = &pci_dev_ops_pci,
-};
-
-static const struct pci_driver gec_driver __pci_driver = {
-	.ops = &gec_ops,
-	.vendor = PCI_VID_ATI,
-	.device = PCI_DID_ATI_SB800_GEC,
-};
-
-/**
- *  Fill build time defaults.
- */
-static void sb800_init(void *chip_info)
-{
-	printk(BIOS_DEBUG, "SB800: %s\n", __func__);
-	sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry;
-	sb800_cimx_config(sb_config);
-
-	/* Initially enable all GPP ports 0 to 3 */
-	abcfg_reg(0xc0, 0x01FF, 0x0F4);
-}
-
-/**
- * South Bridge CIMx ramstage entry point wrapper.
- */
-void sb_Before_Pci_Init(void)
-{
-	printk(BIOS_DEBUG, "SB800: %s\n", __func__);
-	sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
-	AmdSbDispatcher(sb_config);
-}
-
-void sb_After_Pci_Init(void)
-{
-	printk(BIOS_DEBUG, "SB800: %s\n", __func__);
-	sb_config->StdHeader.Func = SB_AFTER_PCI_INIT;
-	AmdSbDispatcher(sb_config);
-}
-
-void sb_Mid_Post_Init(void)
-{
-	printk(BIOS_DEBUG, "SB800: %s\n", __func__);
-	sb_config->StdHeader.Func = SB_MID_POST_INIT;
-	AmdSbDispatcher(sb_config);
-}
-
-void sb_Late_Post(void)
-{
-	printk(BIOS_DEBUG, "SB800: %s\n", __func__);
-	sb_config->StdHeader.Func = SB_LATE_POST_INIT;
-	AmdSbDispatcher(sb_config);
-}
-
-void sb_Before_Pci_Restore_Init(void)
-{
-	printk(BIOS_DEBUG, "SB800: %s\n", __func__);
-	sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT;
-	AmdSbDispatcher(sb_config);
-}
-
-void sb_After_Pci_Restore_Init(void)
-{
-	printk(BIOS_DEBUG, "SB800: %s\n", __func__);
-	sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT;
-	AmdSbDispatcher(sb_config);
-}
-
-/*
- * Update the PCI devices with a valid IRQ number
- * that is set in the mainboard PCI_IRQ structures.
- */
-static void set_pci_irqs(void *unused)
-{
-	/* Write PCI_INTR regs 0xC00/0xC01 */
-	write_pci_int_table();
-
-	/* Write IRQs for all devicetree enabled devices */
-	write_pci_cfg_irqs();
-}
-
-/*
- * Hook this function into the PCI state machine
- * on entry into BS_DEV_ENABLE.
- */
-BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
-
-/**
- * @brief SB Cimx entry point sbBeforePciInit wrapper
- */
-static void sb800_enable(struct device *dev)
-{
-	struct southbridge_amd_cimx_sb800_config *sb_chip =
-		(struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
-
-	switch (dev->path.pci.devfn) {
-	case PCI_DEVFN(0x11, 0): /* 0:11.0  SATA */
-		if (dev->enabled) {
-			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
-			if (sb_chip->boot_switch_sata_ide == 1)
-				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
-			else if (sb_chip->boot_switch_sata_ide == 0)
-				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
-		} else {
-			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
-		}
-		break;
-
-	case PCI_DEVFN(0x14, 0): /* 0:14:0 SMBUS */
-		/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
-		setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
-		break;
-
-	case PCI_DEVFN(0x14, 1): /* 0:14:1 IDE */
-		break;
-
-	case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */
-		if (dev->enabled) {
-			if (sb_config->AzaliaController == AZALIA_DISABLE) {
-				sb_config->AzaliaController = AZALIA_AUTO;
-			}
-		} else {
-			sb_config->AzaliaController = AZALIA_DISABLE;
-		}
-		break;
-
-	case PCI_DEVFN(0x14, 3): /* 0:14:3 LPC */
-		/* Initialize the fans */
-#if CONFIG(SB800_IMC_FAN_CONTROL)
-		init_sb800_IMC_fans(dev);
-#elif CONFIG(SB800_MANUAL_FAN_CONTROL)
-		init_sb800_MANUAL_fans(dev);
-#endif
-		break;
-
-	case PCI_DEVFN(0x14, 4): /* 0:14:4 PCI */
-		/* PcibConfig [PM_Reg: EAh], PCIDisable [Bit0]
-		 * 'PCIDisable' set to 0 to enable P2P bridge.
-		 * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
-		 *              to function as GPIO {GPIO 35:0}.
-		 */
-		if (!sb_chip->disconnect_pcib && dev->enabled)
-			pm_write8(0xea, pm_read8(0xea) & 0xfe);
-		else
-			pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
-		break;
-
-	case PCI_DEVFN(0x14, 6): /* 0:14:6 GEC */
-		if (dev->enabled) {
-			sb_config->GecConfig = 0;
-		} else {
-			sb_config->GecConfig = 1;
-		}
-		break;
-
-	case PCI_DEVFN(0x15, 0): /* 0:15:0 PCIe PortA */
-		{
-			struct device *device;
-			for (device = dev; device; device = device->sibling) {
-				if ((device->path.pci.devfn & ~3) != PCI_DEVFN(0x15, 0)) break;
-				sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
-			}
-
-			/*
-			 * GPP_CFGMODE_X4000: PortA Lanes[3:0]
-			 * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
-			 * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
-			 * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
-			 */
-			sb_config->GppLinkConfig = sb_chip->gpp_configuration;
-		}
-		break;
-
-	case PCI_DEVFN(0x12, 0): /* 0:12:0 OHCI-USB1 */
-		sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
-		break;
-	case PCI_DEVFN(0x12, 2): /* 0:12:2 EHCI-USB1 */
-		sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled;
-		break;
-	case PCI_DEVFN(0x13, 0): /* 0:13:0 OHCI-USB2 */
-		sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled;
-		break;
-	case PCI_DEVFN(0x13, 2): /* 0:13:2 EHCI-USB2 */
-		sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled;
-		break;
-	case PCI_DEVFN(0x14, 5): /* 0:14:5 OHCI-USB4 */
-		sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled;
-		break;
-	case PCI_DEVFN(0x16, 0): /* 0:16:0 OHCI-USB3 */
-		sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled;
-		break;
-	case PCI_DEVFN(0x16, 2): /* 0:16:2 EHCI-USB3 */
-		sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
-
-		/* FIXME: Find better callsites for these.
-		 * call the CIMX entry at the last sb800 device,
-		 * so make sure the mainboard devicetree is complete
-		 */
-		if (!acpi_is_wakeup_s3())
-			sb_Before_Pci_Init();
-		else
-			sb_Before_Pci_Restore_Init();
-		break;
-
-	default:
-		break;
-	}
-}
-
-struct chip_operations southbridge_amd_cimx_sb800_ops = {
-	CHIP_NAME("ATI SB800")
-	.init = sb800_init,
-	.enable_dev = sb800_enable,
-};
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c
deleted file mode 100644
index 12a21d2f36..0000000000
--- a/src/southbridge/amd/cimx/sb800/lpc.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_def.h>
-#include <arch/ioapic.h>
-#include "lpc.h"
-#include <device/pci_ops.h>
-
-void lpc_read_resources(struct device *dev)
-{
-	struct resource *res;
-
-	printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__);
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
-
-	/* Add an extra subtractive resource for both memory and I/O. */
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->base = 0;
-	res->size = 0x1000;
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->base = 0xff800000;
-	res->size = 0x00800000; /* 8 MB for flash */
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	/* Add a memory resource for the SPI BAR. */
-	mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB);
-
-	res = new_resource(dev, 3);
-	res->base = IO_APIC_ADDR;
-	res->size = 0x00001000;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	compact_resources(dev);
-	printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__);
-}
-
-void lpc_set_resources(struct device *dev)
-{
-	struct resource *res;
-
-	printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__);
-
-	/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
-	res = find_resource(dev, 2);
-	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
-
-	pci_dev_set_resources(dev);
-
-	printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__);
-}
-
-/**
- * @brief Enable resources for children devices
- *
- * @param dev the device whose children's resources are to be enabled
- *
- */
-void lpc_enable_childrens_resources(struct device *dev)
-{
-	struct bus *link;
-	u32 reg, reg_x;
-	int var_num = 0;
-	u16 reg_var[3];
-
-	printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__);
-	reg = pci_read_config32(dev, 0x44);
-	reg_x = pci_read_config32(dev, 0x48);
-
-	for (link = dev->link_list; link; link = link->next) {
-		struct device *child;
-		for (child = link->children; child;
-		     child = child->sibling) {
-			if (child->enabled
-			    && (child->path.type == DEVICE_PATH_PNP)) {
-				struct resource *res;
-				for (res = child->resource_list; res; res = res->next) {
-					u32 base; /* don't need long long */
-					if (!(res->flags & IORESOURCE_IO))
-						continue;
-					base = res->base;
-/*
-					printk(BIOS_DEBUG, "sb800 lpc decode:%s,
-					       base=0x%08x, end=0x%08x\n",
-					       dev_path(child), base,
-					       resource_end(res));
-*/
-					switch (base) {
-					case 0x60:	/*  KB */
-					case 0x64:	/*  MS */
-						reg |= (1 << 29);
-						break;
-					case 0x3f8:	/*  COM1 */
-						reg |= (1 << 6);
-						break;
-					case 0x2f8:	/*  COM2 */
-						reg |= (1 << 7);
-						break;
-					case 0x378:	/*  Parallel 1 */
-						reg |= (1 << 0);
-						break;
-					case 0x3f0:	/*  FD0 */
-						reg |= (1 << 26);
-						break;
-					case 0x220:	/*  Audio 0 */
-						reg |= (1 << 8);
-						break;
-					case 0x300:	/*  Midi 0 */
-						reg |= (1 << 18);
-						break;
-					case 0x400:
-						reg_x |= (1 << 16);
-						break;
-					case 0x480:
-						reg_x |= (1 << 17);
-						break;
-					case 0x500:
-						reg_x |= (1 << 18);
-						break;
-					case 0x580:
-						reg_x |= (1 << 19);
-						break;
-					case 0x4700:
-						reg_x |= (1 << 22);
-						break;
-					case 0xfd60:
-						reg_x |= (1 << 23);
-						break;
-					default:
-						if (var_num >= 3)
-							continue;	/* only 3 var ; compact them ? */
-						switch (var_num) {
-						case 0:
-							reg_x |= (1 << 2);
-							break;
-						case 1:
-							reg_x |= (1 << 24);
-							break;
-						case 2:
-							reg_x |= (1 << 25);
-							break;
-						}
-						reg_var[var_num++] =
-						    base & 0xffff;
-					}
-				}
-			}
-		}
-	}
-	pci_write_config32(dev, 0x44, reg);
-	pci_write_config32(dev, 0x48, reg_x);
-	/* Set WideIO for as many IOs found (fall through is on purpose) */
-	switch (var_num) {
-	case 3:
-		pci_write_config16(dev, 0x90, reg_var[2]);
-		__fallthrough;
-	case 2:
-		pci_write_config16(dev, 0x66, reg_var[1]);
-		__fallthrough;
-	case 1:
-		//pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
-		break;
-	}
-	printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__);
-}
diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h
deleted file mode 100644
index 809ff7fd4e..0000000000
--- a/src/southbridge/amd/cimx/sb800/lpc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SB800_LPC_H_
-#define _SB800_LPC_H_
-
-#define SPIROM_BASE_ADDRESS_REGISTER  0xA0
-#define SPI_ROM_ENABLE                0x02
-#define SPI_BASE_ADDRESS              0xFEC10000
-
-void lpc_read_resources(struct device *dev);
-void lpc_set_resources(struct device *dev);
-void lpc_enable_childrens_resources(struct device *dev);
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb800/pci_devs.h b/src/southbridge/amd/cimx/sb800/pci_devs.h
deleted file mode 100644
index 91825ba16e..0000000000
--- a/src/southbridge/amd/cimx/sb800/pci_devs.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _CIMX_SB800_PCI_DEVS_H_
-#define _CIMX_SB800_PCI_DEVS_H_
-
-#include <device/pci_def.h>
-
-#define BUS0			0
-
-/* SATA */
-#define SATA_DEV		0x11
-#define SATA_FUNC		0
-#define SATA_IDE_DEVID		0x4390
-#define AHCI_DEVID		0x4391
-#define RAID_DEVID		0x4392
-#define RAID5_DEVID		0x4393
-#define SATA_DEVFN		PCI_DEVFN(SATA_DEV, SATA_FUNC)
-
-/* OHCI */
-#define OHCI1_DEV		0x12
-#define OHCI1_FUNC		0
-#define OHCI2_DEV		0x13
-#define OHCI2_FUNC		0
-#define OHCI3_DEV		0x16
-#define OHCI3_FUNC		0
-#define OHCI4_DEV		0x14
-#define OHCI4_FUNC		5
-#define OHCI_DEVID		0x4397
-#define OHCI1_DEVFN		PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC)
-#define OHCI2_DEVFN		PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC)
-#define OHCI3_DEVFN		PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC)
-#define OHCI4_DEVFN		PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC)
-
-/* EHCI */
-#define EHCI1_DEV		0x12
-#define EHCI1_FUNC		2
-#define EHCI2_DEV		0x13
-#define EHCI2_FUNC		2
-#define EHCI3_DEV		0x16
-#define EHCI3_FUNC		2
-#define EHCI_DEVID 0x4396
-#define EHCI1_DEVFN		PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC)
-#define EHCI2_DEVFN		PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC)
-#define EHCI3_DEVFN		PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC)
-
-/* Fusion Controller Hub */
-#define SMBUS_DEV		0x14
-#define SMBUS_FUNC		0
-#define SMBUS_DEVID		0x4385
-#define SMBUS_DEVFN		PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
-
-/* IDE */
-#define IDE_DEV			0x14
-#define IDE_FUNC		1
-#define IDE_DEVID		0x439C
-#define IDE_DEVFN		PCI_DEVFN(IDE_DEV, IDE_FUNC)
-
-/* HD Audio */
-#define HDA_DEV			0x14
-#define HDA_FUNC		2
-#define HDA_DEVID		0x4383
-#define HDA_DEVFN		PCI_DEVFN(HDA_DEV, HDA_FUNC)
-
-/* LPC BUS */
-#define PCU_DEV			0x14
-#define LPC_DEV			PCU_DEV
-#define LPC_FUNC		3
-#define LPC_DEVID		0x439D
-#define LPC_DEVFN		PCI_DEVFN(LPC_DEV, LPC_FUNC)
-
-/* PCI Ports */
-#define SB_PCI_PORT_DEV		0x14
-#define SB_PCI_PORT_FUNC	4
-#define SB_PCI_PORT_DEVID	0x4384
-#define SB_PCI_PORT_DEVFN	PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC)
-
-/* PCIe Ports */
-#define SB_PCIE_DEV		0x15
-#define SB_PCIE_PORT1_FUNC	0
-#define SB_PCIE_PORT2_FUNC	1
-#define SB_PCIE_PORT3_FUNC	2
-#define SB_PCIE_PORT4_FUNC	3
-#define SB_PCIE_PORT1_DEVID	0x43A0
-#define SB_PCIE_PORT2_DEVID	0x43A1
-#define SB_PCIE_PORT3_DEVID	0x43A2
-#define SB_PCIE_PORT4_DEVID	0x43A3
-#define SB_PCIE_PORT1_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC)
-#define SB_PCIE_PORT2_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC)
-#define SB_PCIE_PORT3_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC)
-#define SB_PCIE_PORT4_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC)
-
-#endif /* _CIMX_SB800_PCI_DEVS_H_ */
diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c
deleted file mode 100644
index 483716c202..0000000000
--- a/src/southbridge/amd/cimx/sb800/ramtop.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <acpi/acpi.h>
-#include "SBPLATFORM.h"
-
-int acpi_get_sleep_type(void)
-{
-	u16 tmp = inw(PM1_CNT_BLK_ADDRESS);
-	tmp = ((tmp & (7 << 10)) >> 10);
-	return (int)tmp;
-}
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
deleted file mode 100644
index 6c8f0e426c..0000000000
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
-#include <device/pci_ops.h>
-#include <cf9_reset.h>
-#include <reset.h>
-
-#define HT_INIT_CONTROL		0x6c
-#define HTIC_BIOSR_Detect	(1 << 5)
-
-#define DEV_CDB 0x18
-#define NODE_PCI(x, fn)	(((DEV_CDB + x) < 32) ? (PCI_DEV(0, (DEV_CDB + x), fn)) : (PCI_DEV((0 - 1), (DEV_CDB + x - 32), fn)))
-
-void cf9_reset_prepare(void)
-{
-	u32 nodes;
-	u32 htic;
-	pci_devfn_t dev;
-	int i;
-
-	nodes = ((pci_read_config32(PCI_DEV(0, DEV_CDB, 0), 0x60) >> 4) & 7) + 1;
-	for (i = 0; i < nodes; i++) {
-		dev = NODE_PCI(i, 0);
-		htic = pci_read_config32(dev, HT_INIT_CONTROL);
-		htic &= ~HTIC_BIOSR_Detect;
-		pci_write_config32(dev, HT_INIT_CONTROL, htic);
-	}
-}
-
-void do_board_reset(void)
-{
-	system_reset();
-}
diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h
deleted file mode 100644
index 5e5ca5d5f5..0000000000
--- a/src/southbridge/amd/cimx/sb800/sb_cimx.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _CIMX_H_
-#define _CIMX_H_
-
-/**
- * AMD South Bridge CIMx entry point wrapper
- */
-void sb_Poweron_Init(void);
-void sb_Before_Pci_Init(void);
-void sb_After_Pci_Init(void);
-void sb_Mid_Post_Init(void);
-void sb_Late_Post(void);
-void sb_Before_Pci_Restore_Init(void);
-void sb_After_Pci_Restore_Init(void);
-
-/**
- * CIMX not set the clock to 48Mhz until sbBeforePciInit,
- * coreboot may need to set this even more earlier
- */
-void sb800_clk_output_48Mhz(void);
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c
deleted file mode 100644
index 50c77cf0b0..0000000000
--- a/src/southbridge/amd/cimx/sb800/smbus.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/io.h>
-#include <stdint.h>
-#include "smbus.h"
-#include <console/console.h>
-
-static int smbus_wait_until_ready(u32 smbus_io_base)
-{
-	u32 loops;
-
-	loops = SMBUS_TIMEOUT;
-	do {
-		u8 val;
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f;
-		if (val == 0) {	/* ready now */
-			return 0;
-		}
-		outb(val, smbus_io_base + SMBHSTSTAT);
-	} while (--loops);
-
-	return -2;		/* time out */
-}
-
-static int smbus_wait_until_done(u32 smbus_io_base)
-{
-	u32 loops;
-
-	loops = SMBUS_TIMEOUT;
-	do {
-		u8 val;
-
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f;	/* mask off reserved bits */
-		if (val & 0x1c) {
-			return -5;	/* error */
-		}
-		if (val == 0x02) {
-			outb(val, smbus_io_base + SMBHSTSTAT);	/* clear status */
-			return 0;
-		}
-	} while (--loops);
-
-	return -3;		/* timeout */
-}
-
-int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__);
-		return -2;	/* not ready */
-	}
-
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__);
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTCMD);
-
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__);
-	return byte;
-}
-
-int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__);
-		return -2;	/* not ready */
-	}
-
-	 printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__);
-	/* set the command... */
-	outb(val, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__);
-	return 0;
-}
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__);
-		return -2;	/* not ready */
-	}
-
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__);
-	/* set the command/address... */
-	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTDAT0);
-
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__);
-	return byte;
-}
-
-int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__);
-		return -2;	/* not ready */
-	}
-
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__);
-	/* set the command/address... */
-	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
-
-	/* output value */
-	outb(val, smbus_io_base + SMBHSTDAT0);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__);
-	return 0;
-}
-
-void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
-{
-	u32 tmp;
-
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__);
-	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
-	tmp = inl(AB_DATA);
-	/* rpr 4.2
-	 * For certain revisions of the chip, the ABCFG registers,
-	 * with an address of 0x100NN (where 'N' is any hexadecimal
-	 * number), require an extra programming step.*/
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
-	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__);
-}
-
-void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
-{
-	u32 tmp;
-
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__);
-	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
-	tmp = inl(AB_DATA);
-	/* rpr 4.2
-	 * For certain revisions of the chip, the ABCFG registers,
-	 * with an address of 0x100NN (where 'N' is any hexadecimal
-	 * number), require an extra programming step.*/
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
-	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__);
-}
-
-/* space = 0: AX_INDXC, AX_DATAC
- * space = 1: AX_INDXP, AX_DATAP
- */
-void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val)
-{
-	u32 tmp;
-
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__);
-	/* read axindc to tmp */
-	outl(space << 29 | space << 3 | 0x30, AB_INDX);
-	outl(axindc, AB_DATA);
-	outl(0, AB_INDX);
-	outl(space << 29 | space << 3 | 0x34, AB_INDX);
-	tmp = inl(AB_DATA);
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	/* write tmp */
-	outl(space << 29 | space << 3 | 0x30, AB_INDX);
-	outl(axindc, AB_DATA);
-	outl(0, AB_INDX);
-	outl(space << 29 | space << 3 | 0x34, AB_INDX);
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-	printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__);
-}
diff --git a/src/southbridge/amd/cimx/sb800/smbus.h b/src/southbridge/amd/cimx/sb800/smbus.h
deleted file mode 100644
index dfd55f87ea..0000000000
--- a/src/southbridge/amd/cimx/sb800/smbus.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SB800_SMBUS_H_
-#define _SB800_SMBUS_H_
-
-#include <stdint.h>
-
-#define SMBUS_IO_BASE	SMBUS0_BASE_ADDRESS
-
-#define SMBHSTSTAT		0x0
-#define SMBSLVSTAT		0x1
-#define SMBHSTCTRL		0x2
-#define SMBHSTCMD		0x3
-#define SMBHSTADDR		0x4
-#define SMBHSTDAT0		0x5
-#define SMBHSTDAT1		0x6
-#define SMBHSTBLKDAT		0x7
-
-#define SMBSLVCTRL		0x8
-#define SMBSLVCMD_SHADOW	0x9
-#define SMBSLVEVT		0xa
-#define SMBSLVDAT		0xc
-
-#define AB_INDX			0xcd8
-#define AB_DATA			(AB_INDX + 4)
-
-/* Between 1-10 seconds, We should never timeout normally
- * Longer than this is just painful when a timeout condition occurs.
- */
-#define SMBUS_TIMEOUT (100 * 1000 * 10)
-
-#define abcfg_reg(reg, mask, val)	\
-	alink_ab_indx((ABCFG), (reg), (mask), (val))
-#define axcfg_reg(reg, mask, val)	\
-	alink_ab_indx((AXCFG), (reg), (mask), (val))
-#define axindxc_reg(reg, mask, val)	\
-	alink_ax_indx((AX_INDXC), (reg), (mask), (val))
-#define axindxp_reg(reg, mask, val)		\
-	alink_ax_indx((AX_INDXP), (reg), (mask), (val))
-#define rcindxc_reg(reg, port, mask, val)	\
-	alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
-#define rcindxp_reg(reg, port, mask, val)	\
-	alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
-int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
-int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
-void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
-void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
-void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val);
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c
deleted file mode 100644
index 35c1cccdb4..0000000000
--- a/src/southbridge/amd/cimx/sb800/smbus_spd.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci_def.h>
-#include <device/device.h>
-#include <stddef.h>
-#include <OEM.h>		/* SMBUS0_BASE_ADDRESS */
-
-/* warning: Porting.h includes an open #pragma pack(1) */
-#include <vendorcode/amd/include/Porting.h>
-#include <AGESA.h>
-#include "chip.h"
-#include "smbus_spd.h"
-
-#include <northbridge/amd/agesa/dimmSpd.h>
-
-/* uncomment for source level debug - GDB gets really confused otherwise. */
-//#pragma optimize ("", off)
-
-/**
- *	Read a single SPD byte.  If the first byte is being read, set up the
- *	address and offset. Following bytes auto increment.
- */
-static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer,
-						   int offset, int initial_offset)
-{
-	unsigned int status = -1;
-	UINT64 time_limit;
-
-	/* clear status register */
-	__outbyte(iobase + SMBUS_STATUS_REG, 0x1E);
-
-	if (offset == initial_offset) {
-		/* Clear slave status, set offset, set slave address and start reading */
-		__outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x3E);
-		__outbyte(iobase + SMBUS_CONTROL_REG, offset);
-		__outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT);
-		__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND);
-	} else {
-		/* Issue read command - auto increments to next byte */
-		__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND);
-	}
-	/* time limit to avoid hanging for unexpected error status */
-	time_limit = __rdtsc() + MAX_READ_TSC_COUNT;
-	while (__rdtsc() <= time_limit) {
-		status = __inbyte(iobase + SMBUS_STATUS_REG);
-		if ((status & SMBUS_INTERRUPT_MASK) == 0)
-			continue;	/* SMBusInterrupt not set, keep waiting */
-		if ((status & HOSTBUSY_MASK) != 0)
-			continue;	/* HostBusy set, keep waiting */
-		break;
-	}
-
-	if (status != STATUS__COMPLETED_SUCCESSFULLY)
-		return AGESA_ERROR;
-
-	buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG);
-	return AGESA_SUCCESS;
-}
-
-static void writePmReg(UINT8 reg, UINT8 data)
-{
-	__outbyte(PMIO_INDEX_REG, reg);
-	__outbyte(PMIO_DATA_REG, data);
-}
-
-static void setupFch(UINT16 ioBase)
-{
-	/* set up SMBUS - Set to SMBUS 0 & set base address */
-	/* For SB800 & Hudson1 to SB900 & Hudson 2/3 */
-	writePmReg(SMBUS_BAR_HIGH_BYTE, ioBase >> 8);
-	writePmReg(SMBUS_BAR_LOW_BYTE, (ioBase & 0xe0) | 1);
-
-	/* set SMBus clock to 400 KHz */
-	__outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000);
-}
-
-/**
- *	Read one or more SPD bytes from a DIMM.
- *	Start with offset zero and read sequentially.
- *	Reads 128 bytes in 7-8 ms at 400 KHz.
- */
-static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer,
-					 UINT16 count)
-{
-	UINT16 index;
-	UINT8 status;
-	UINT8 initial_offset = 0;
-
-	setupFch(iobase);
-
-	for (index = initial_offset; index < count; index++) {
-		status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index,
-				initial_offset);
-		if (status != AGESA_SUCCESS)
-			return status;
-	}
-
-	return status;
-}
-
-int smbus_readSpd(int spdAddress, char *buf, size_t len)
-{
-	int ioBase = SMBUS0_BASE_ADDRESS;
-	setupFch(ioBase);
-	return readspd(ioBase, spdAddress, buf, len);
-}
diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.h b/src/southbridge/amd/cimx/sb800/smbus_spd.h
deleted file mode 100644
index e3fbd092e6..0000000000
--- a/src/southbridge/amd/cimx/sb800/smbus_spd.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SMBUS_SPD_H_
-#define _SMBUS_SPD_H_
-
-#define READ_BIT				0x01
-
-#define SMBUS_INTERRUPT_MASK	0x02
-#define HOSTBUSY_MASK			0x01
-
-#define SMBUS_READ_BYTE_COMMAND	0x48
-#define SMBUS_READ_COMMAND		0x44
-
-#define MAX_READ_TSC_COUNT		(2000000000 / 10)
-
-#define PMIO_INDEX_REG			0xCD6
-#define PMIO_DATA_REG			0xCD7
-
-#define SMBUS_BAR_LOW_BYTE		0x2C
-#define SMBUS_BAR_HIGH_BYTE		0x2D
-
-#define SMBUS_STATUS_REG		0x00
-#define SMBUS_SLAVE_STATUS_REG	0x01
-#define SMBUS_COMMAND_REG		0x02
-#define SMBUS_CONTROL_REG		0x03
-#define SMBUS_HOST_CMD_REG		0x04
-#define SMBUS_DATA0_REG			0x05
-#define SMBUS_CLOCK_REG			0x0E
-
-#define STATUS__COMPLETED_SUCCESSFULLY	0x02
-
-#define SMBUS_FREQUENCY_CONST	66000000 / 4
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
deleted file mode 100644
index 792a4a1d7e..0000000000
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/mmio.h>
-#include <console/console.h>
-#include <spi_flash.h>
-#include <spi-generic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <types.h>
-
-#include "SBPLATFORM.h"
-#include <vendorcode/amd/cimx/sb800/ECfan.h>
-
-#define AMD_SB_SPI_TX_LEN	8
-
-static uintptr_t spibar;
-
-static void reset_internal_fifo_pointer(void)
-{
-	do {
-		write8((void *)(spibar + 2),
-		       read8((void *)(spibar + 2)) | 0x10);
-	} while (read8((void *)(spibar + 0xD)) & 0x7);
-}
-
-static void execute_command(void)
-{
-	write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1);
-
-	while ((read8((void *)(spibar + 2)) & 1) &&
-	       (read8((void *)(spibar + 3)) & 0x80));
-}
-
-void spi_init(void)
-{
-	struct device *dev;
-
-	dev = pcidev_on_root(0x14, 3);
-	spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
-}
-
-static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
-		size_t bytesout, void *din, size_t bytesin)
-{
-	/* First byte is cmd which can not be sent through FIFO. */
-	u8 cmd = *(u8 *)dout++;
-	u8 readoffby1;
-	u8 readwrite;
-	size_t count;
-
-	bytesout--;
-
-	/*
-	 * Check if this is a write command attempting to transfer more bytes
-	 * than the controller can handle. Iterations for writes are not
-	 * supported here because each SPI write command needs to be preceded
-	 * and followed by other SPI commands, and this sequence is controlled
-	 * by the SPI chip driver.
-	 */
-	if (bytesout > AMD_SB_SPI_TX_LEN) {
-		printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use"
-		     " spi_crop_chunk()?\n");
-		return -1;
-	}
-
-	readoffby1 = bytesout ? 0 : 1;
-
-	readwrite = (bytesin + readoffby1) << 4 | bytesout;
-	write8((void *)(spibar + 1), readwrite);
-	write8((void *)(spibar + 0), cmd);
-
-	reset_internal_fifo_pointer();
-	for (count = 0; count < bytesout; count++, dout++) {
-		write8((void *)(spibar + 0x0C), *(u8 *)dout);
-	}
-
-	reset_internal_fifo_pointer();
-	execute_command();
-
-	reset_internal_fifo_pointer();
-	/* Skip the bytes we sent. */
-	for (count = 0; count < bytesout; count++) {
-		read8((void *)(spibar + 0x0C));
-	}
-
-	reset_internal_fifo_pointer();
-	for (count = 0; count < bytesin; count++, din++) {
-		*(u8 *)din = read8((void *)(spibar + 0x0C));
-	}
-
-	return 0;
-}
-
-static void ImcSleep(void)
-{
-	u8	cmd_val = 0x96;		/* Kick off IMC Mailbox command 96 */
-	u8	reg0_val = 0;		/* clear response register */
-	u8	reg1_val = 0xB4;	/* request ownership flag */
-
-	WriteECmsg(MSG_REG0, AccWidthUint8, &reg0_val);
-	WriteECmsg(MSG_REG1, AccWidthUint8, &reg1_val);
-	WriteECmsg(MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val);
-
-	WaitForEcLDN9MailboxCmdAck();
-}
-
-static void ImcWakeup(void)
-{
-	u8	cmd_val = 0x96;		/* Kick off IMC Mailbox command 96 */
-	u8	reg0_val = 0;		/* clear response register */
-	u8	reg1_val = 0xB5;	/* release ownership flag */
-
-	WriteECmsg(MSG_REG0, AccWidthUint8, &reg0_val);
-	WriteECmsg(MSG_REG1, AccWidthUint8, &reg1_val);
-	WriteECmsg(MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val);
-
-	WaitForEcLDN9MailboxCmdAck();
-}
-
-int chipset_volatile_group_begin(const struct spi_flash *flash)
-{
-	if (!CONFIG(SB800_IMC_FWM))
-		return 0;
-
-	ImcSleep();
-	return 0;
-}
-
-int chipset_volatile_group_end(const struct spi_flash *flash)
-{
-	if (!CONFIG(SB800_IMC_FWM))
-		return 0;
-
-	ImcWakeup();
-	return 0;
-}
-
-static int xfer_vectors(const struct spi_slave *slave,
-			struct spi_op vectors[], size_t count)
-{
-	return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);
-}
-
-static const struct spi_ctrlr spi_ctrlr = {
-	.xfer_vector = xfer_vectors,
-	.max_xfer_size = AMD_SB_SPI_TX_LEN,
-	.flags = SPI_CNTRLR_DEDUCT_CMD_LEN,
-};
-
-const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
-	{
-		.ctrlr = &spi_ctrlr,
-		.bus_start = 0,
-		.bus_end = 0,
-	},
-};
-
-const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc
index ca6c75647c..e086dc3a20 100644
--- a/src/southbridge/amd/common/Makefile.inc
+++ b/src/southbridge/amd/common/Makefile.inc
@@ -1,5 +1 @@
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += amd_pci_util.c
diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl
index 9a2c7445db..10f25a1ef8 100644
--- a/src/southbridge/amd/pi/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl
@@ -144,9 +144,4 @@ Method(_INI, 0) {
 	/* DBGO(\_REV) */
 	/* DBGO("\n") */
 
-#if CONFIG(HUDSON_IMC_FWM)
-#if CONFIG(ACPI_ENABLE_THERMAL_ZONE)
-	ITZE() /* enable IMC Fan Control*/
-#endif
-#endif
 } /* End Method(_SB._INI) */
diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c
index e9b26e0ad0..1e9864a2ee 100644
--- a/src/southbridge/amd/pi/hudson/hudson.c
+++ b/src/southbridge/amd/pi/hudson/hudson.c
@@ -88,8 +88,7 @@ static void hudson_final(void *chip_info)
 {
 	if (CONFIG(HUDSON_IMC_FWM)) {
 		agesawrapper_fchecfancontrolservice();
-		if (!CONFIG(ACPI_ENABLE_THERMAL_ZONE))
-			enable_imc_thermal_zone();
+		enable_imc_thermal_zone();
 	}
 }
author	Arthur Heymans <arthur@aheymans.xyz>	2022-11-01 23:38:19 +0100
committer	Arthur Heymans <arthur@aheymans.xyz>	2022-11-07 13:59:17 +0000
commit	03a6ccd20d9bb54e3a009269b8e454ee8a2e3051 (patch)
tree	8f8b9c6fc6e383e5e7aa4f9631119a8517859d04 /src/southbridge/amd
parent	1a010236cf922fc28cfb36b604bdf17a9ea3cb82 (diff)