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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-14 19:17:35 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-26 06:52:08 +0000
commite874b1c1794406aa9adcd00a06cdb713b50b88ff (patch)
treec40ca4883c18bc90f0ab05797ff701f90fd9a34a /src/southbridge/amd
parent6f1754d090e79f6e4d06780a494b62a83a5d8fcc (diff)
cpu/intel/common: implement the two missing CPPC v2 autonomous registers
This implements the two missing registers for the CPPC Hardware Autonomous mode (HWP) to the CPPC v2 package. The right values can be determined via Intel SDM and the ACPI 6.3 spec. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt Delco <delco@chromium.org>
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