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| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2016-11-21 17:59:38 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-23 22:49:51 +0100 |
| commit | 6fca307ced326e311a3a6d81b7a4fed6429b4865 (patch) | |
| tree | 1bb5db332e902c9f98935285369590a2bfac7d14 /src/southbridge/amd | |
| parent | 8883e0f126fdc86ca00590cbbfb7c5c876e0fceb (diff) | |
google/pyro: Update DPTF settings
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
CPU passive point:57, critical point:90
TSR1 passive point:55, critial point:70
TSR2 passive point:65, critial point:80
2. Update DPTF TRT Sample Period.
CPU: 5s
TSR0: 50s
TSR1: 55s
TSR2: 120s
BUG=none
BRANCH=master
TEST=emerge-pyro coreboot
Change-Id: Ib1b4b31a49d9396b1c5c9dd8d0b9b9998d01744f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17552
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/amd')
0 files changed, 0 insertions, 0 deletions