sb/amd/{agesa,pi,cimx}/bootblock: Use simple PCI config accessor

Change-Id: I5e1f2ceda37927d7a75660affee8504f9f8aff15
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37597
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 23 insertions, 23 deletions

diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index 517b928d8d..2fa0da61e8 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -36,15 +36,15 @@ static void hudson_enable_rom(void)
 	dev = PCI_DEV(0, 0x14, 3);
 
 	/* Decode variable LPC ROM address ranges 1 and 2. */
-	reg8 = pci_io_read_config8(dev, 0x48);
+	reg8 = pci_s_read_config8(dev, 0x48);
 	reg8 |= (1 << 3) | (1 << 4);
-	pci_io_write_config8(dev, 0x48, reg8);
+	pci_s_write_config8(dev, 0x48, reg8);
 
 	/* LPC ROM address range 1: */
 	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
-	pci_io_write_config16(dev, 0x68, 0x000e);
+	pci_s_write_config16(dev, 0x68, 0x000e);
 	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
-	pci_io_write_config16(dev, 0x6a, 0x000f);
+	pci_s_write_config16(dev, 0x6a, 0x000f);
 
 	/* LPC ROM address range 2: */
 	/*
@@ -54,9 +54,9 @@ static void hudson_enable_rom(void)
 	 * 0xffe0(0000): 2MB
 	 * 0xffc0(0000): 4MB
 	 */
-	pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+	pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
 	/* Enable LPC ROM range end at 0xffff(ffff). */
-	pci_io_write_config16(dev, 0x6e, 0xffff);
+	pci_s_write_config16(dev, 0x6e, 0xffff);
 }
 
 void bootblock_early_southbridge_init(void)
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index d42e7eef1d..5decebfac4 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -29,11 +29,11 @@ static void enable_rom(void)
 	 * BIT29: Port Enable for KBC port 0x60 and 0x64
 	 * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
 	 */
-	dword = pci_io_read_config32(dev, 0x44);
+	dword = pci_s_read_config32(dev, 0x44);
 	//dword |= (1<<6) | (1<<29) | (1<<30);
 	/* Turn on all of LPC IO Port decode enable */
 	dword = 0xffffffff;
-	pci_io_write_config32(dev, 0x44, dword);
+	pci_s_write_config32(dev, 0x44, dword);
 
 	/* SB800 LPC Bridge 0:20:3:48h.
 	 * BIT0: Port Enable for SuperIO 0x2E-0x2F
@@ -42,14 +42,14 @@ static void enable_rom(void)
 	 * BIT6: Port Enable for RTC IO 0x70-0x73
 	 * BIT21: Port Enable for Port 0x80
 	 */
-	dword = pci_io_read_config32(dev, 0x48);
+	dword = pci_s_read_config32(dev, 0x48);
 	dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
-	pci_io_write_config32(dev, 0x48, dword);
+	pci_s_write_config32(dev, 0x48, dword);
 
 	/* Enable ROM access */
-	word = pci_io_read_config16(dev, 0x6c);
+	word = pci_s_read_config16(dev, 0x6c);
 	word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6);
-	pci_io_write_config16(dev, 0x6c, word);
+	pci_s_write_config16(dev, 0x6c, word);
 }
 
 static void enable_prefetch(void)
@@ -58,8 +58,8 @@ static void enable_prefetch(void)
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
 
 	/* Enable PrefetchEnSPIFromHost */
-	dword = pci_io_read_config32(dev, 0xb8);
-	pci_io_write_config32(dev, 0xb8, dword | (1 << 24));
+	dword = pci_s_read_config32(dev, 0xb8);
+	pci_s_write_config32(dev, 0xb8, dword | (1 << 24));
 }
 
 static void enable_spi_fast_mode(void)
@@ -69,15 +69,15 @@ static void enable_spi_fast_mode(void)
 
 	// set temp MMIO base
 	volatile u32 *spi_base = (void *)0xa0000000;
-	u32 save = pci_io_read_config32(dev, 0xa0);
-	pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2);
+	u32 save = pci_s_read_config32(dev, 0xa0);
+	pci_s_write_config32(dev, 0xa0, (u32) spi_base | 2);
 
 	// early enable of SPI 33 MHz fast mode read
 	dword = spi_base[3];
 	spi_base[3] = (dword & ~(3 << 14)) | (1 << 14);
 	spi_base[0] = spi_base[0] | (1 << 18);	// fast read enable
 
-	pci_io_write_config32(dev, 0xa0, save);
+	pci_s_write_config32(dev, 0xa0, save);
 }
 
 static void enable_clocks(void)
diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c
index 77a4570830..6b7595fc0e 100644
--- a/src/southbridge/amd/pi/hudson/bootblock.c
+++ b/src/southbridge/amd/pi/hudson/bootblock.c
@@ -36,15 +36,15 @@ static void hudson_enable_rom(void)
 	dev = PCI_DEV(0, 0x14, 3);
 
 	/* Decode variable LPC ROM address ranges 1 and 2. */
-	reg8 = pci_io_read_config8(dev, 0x48);
+	reg8 = pci_s_read_config8(dev, 0x48);
 	reg8 |= (1 << 3) | (1 << 4);
-	pci_io_write_config8(dev, 0x48, reg8);
+	pci_s_write_config8(dev, 0x48, reg8);
 
 	/* LPC ROM address range 1: */
 	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
-	pci_io_write_config16(dev, 0x68, 0x000e);
+	pci_s_write_config16(dev, 0x68, 0x000e);
 	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
-	pci_io_write_config16(dev, 0x6a, 0x000f);
+	pci_s_write_config16(dev, 0x6a, 0x000f);
 
 	/* LPC ROM address range 2: */
 	/*
@@ -54,9 +54,9 @@ static void hudson_enable_rom(void)
 	 * 0xffe0(0000): 2MB
 	 * 0xffc0(0000): 4MB
 	 */
-	pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+	pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
 	/* Enable LPC ROM range end at 0xffff(ffff). */
-	pci_io_write_config16(dev, 0x6e, 0xffff);
+	pci_s_write_config16(dev, 0x6e, 0xffff);
 }
 
 void bootblock_early_southbridge_init(void)