diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-28 19:28:19 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-06 09:36:10 +0000 |
| commit | 04506e2987162ec0f280afddd6f4acac070bbf15 (patch) | |
| tree | d555125cd7fc3e726ee9eb730cb2ca320842dc4d /src/southbridge/amd | |
| parent | efea70c0eebba5232ce2bdf3dab8fcd58d8c1c34 (diff) | |
sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I779387fb0c9d3ad6e16d4ccfc39c38dfe6620345
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/late.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 1cf3ae8d00..de91a9af51 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -98,7 +98,7 @@ static void ahci_raid_init(struct device *dev) } dev->command |= PCI_COMMAND_MASTER; - pci_write_config8(dev, PCI_COMMAND, dev->command); + pci_write_config16(dev, PCI_COMMAND, dev->command); printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); } |