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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-08-21 11:37:11 +0300 |
|---|---|---|
| committer | Anton Kochkov <anton.kochkov@gmail.com> | 2012-08-22 05:06:41 +0200 |
| commit | fee73df07ac0d17f319486f977585c7945e0d069 (patch) | |
| tree | 001bb70616c06ef24c267ac257dccc498eac227c /src/southbridge/amd/sr5650 | |
| parent | 0d5d70b79a3824bfa46a7035d901cb0e7672e3fe (diff) | |
Auto-declare chip_operations
The name is derived directly from the device path.
Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Diffstat (limited to 'src/southbridge/amd/sr5650')
| -rw-r--r-- | src/southbridge/amd/sr5650/chip.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/amd/sr5650/chip.h b/src/southbridge/amd/sr5650/chip.h index 43f8dd343c..236ac16b3e 100644 --- a/src/southbridge/amd/sr5650/chip.h +++ b/src/southbridge/amd/sr5650/chip.h @@ -28,7 +28,5 @@ struct southbridge_amd_sr5650_config u8 gpp3a_configuration; /* The configuration of General Purpose Port. */ u16 port_enable; /* Which port is enabled? GPP(2,3,4,5,6,7,9,10,11,12,13) */ }; -struct chip_operations; -extern struct chip_operations southbridge_amd_sr5650_ops; #endif /* SR5650_CHIP_H */ |