summaryrefslogtreecommitdiff
path: root/src/southbridge/amd/sr5650
diff options
context:
space:
mode:
authorStefan Reinauer <reinauer@chromium.org>2012-11-16 13:34:48 -0800
committerPatrick Georgi <patrick@georgi-clan.de>2012-11-20 21:56:05 +0100
commit8ada1526df06cb50a82305e840a5181a3c65575f (patch)
treef1033ee31bdff4add530dedc74b7c537cd175714 /src/southbridge/amd/sr5650
parent82ecf4c582fdab341d88bd80ae3e9a629619c263 (diff)
Unify use of bool config variables
e.g. -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS This will make it easier to switch over to use the config_enabled() macro later on. Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/amd/sr5650')
-rw-r--r--src/southbridge/amd/sr5650/early_setup.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 0f54ba356c..c6131638ad 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -266,7 +266,7 @@ void sr5650_htinit(void)
//set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26);
/* HT Buffer Allocation for Ganged Links!!! */
-#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
+#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
}
}
@@ -299,7 +299,7 @@ void fam10_optimization(void)
}
#else
#define fam10_optimization() do{}while(0)
-#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
+#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
/*****************************************
* Compliant with CIM_33's ATINB_PCICFG_POR_TABLE