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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-09 13:24:14 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-10 15:15:28 +0000 |
| commit | 9646cfe989a096372a717d8ef16ce5096d1b2708 (patch) | |
| tree | ba822c74f89e875382bc9e7bb11b9cf3eaa42753 /src/southbridge/amd/sr5650 | |
| parent | c9f6bd90857d3a7efe08c60f7f5fc19995fb1756 (diff) | |
sb/bd82x6x: Don't rewrite over BCTRL
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not
apply to this PCI bridge because it is only defined for
"Header type 0 (normal devices)" (line 82).
Some lines obove that code line, the "write" on BCTRL is already done.
Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32700
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/sr5650')
0 files changed, 0 insertions, 0 deletions