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| author | Hannah Williams <hannah.williams@intel.com> | 2016-01-26 15:40:24 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-28 20:44:50 +0100 |
| commit | ba6dfe4cc57578cbce1e710c8477d6dda997541a (patch) | |
| tree | 90c557b8cd0fd46588792c25acee1cb29b8d6d95 /src/southbridge/amd/sr5650/sr5650.c | |
| parent | 73600e31992bf115b47de37dcd597b8560b05751 (diff) | |
soc/braswell/acpi: Fix CID1 offset in comment
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I9fd2ebba985362fe8068c10390bb014cf9015ac5
Reviewed-on: https://review.coreboot.org/13483
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/sr5650/sr5650.c')
0 files changed, 0 insertions, 0 deletions