diff options
| author | efdesign98 <efdesign98@gmail.com> | 2011-07-20 12:37:58 -0600 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-07-22 00:20:59 +0200 |
| commit | 00c8c4a31632150fa711493f39e727da950ebe9f (patch) | |
| tree | f3bad2e78ddb6999ad551a73f05c049a266a14ab /src/southbridge/amd/sr5650/sr5650.c | |
| parent | 09ea8ea1a74d56a37755cec52077555b91f9e5b4 (diff) | |
Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/southbridge/amd/sr5650/sr5650.c')
| -rwxr-xr-x[-rw-r--r--] | src/southbridge/amd/sr5650/sr5650.c | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 616ca44ee6..14b919de72 100644..100755 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -266,15 +266,21 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) } /* -* Compliant with CIM_33's ATINB_SetToms. -* Set Top Of Memory below and above 4G. -*/ + * Set Top Of Memory below and above 4G. + */ void sr5650_set_tom(device_t nb_dev) { - extern u64 uma_memory_base; + msr_t sysmem; + + /* The system top memory in SR56X0. */ + sysmem = rdmsr(0xc001001A); + printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo); + pci_write_config32(nb_dev, 0x90, sysmem.lo); - /* set TOM */ - pci_write_config32(nb_dev, 0x90, uma_memory_base); + sysmem = rdmsr(0xc001001D); + printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo); + htiu_write_index(nb_dev, 0x31, sysmem.hi); + htiu_write_index(nb_dev, 0x30, sysmem.lo | 1); } u32 get_vid_did(device_t dev) @@ -308,7 +314,7 @@ void sr5650_nb_pci_table(device_t nb_dev) temp8 &= ~(1<<1); pci_write_config8(nb_dev, 0x8d, temp8); - /* set temporary NB TOM to 0x40000000. */ + /* The system top memory in SR56X0. */ sr5650_set_tom(nb_dev); /* Program NB HTIU table. */ @@ -424,6 +430,11 @@ void sr5650_enable(device_t dev) default: printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); } + + /* Lock HWInit Register after the last device was done */ + if (dev_ind == 13) { + sr56x0_lock_hwinitreg(); + } } struct chip_operations southbridge_amd_sr5650_ops = { |