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author | Ronak Kanabar <ronak.kanabar@intel.com> | 2019-03-16 21:26:43 +0530 |
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committer | Nico Huber <nico.h@gmx.de> | 2019-04-16 14:37:53 +0000 |
commit | a432f38e81cbc392562f80902808e7b27a73c10e (patch) | |
tree | 0f05378e4d057a8873468ac95e905018ea3b0c6a /src/southbridge/amd/sr5650/pcie.c | |
parent | e2f0a5f76c8a525396f627b8ba97e8913ab14fc6 (diff) |
soc/intel/cannonlake: Implement soc side VMX support
Implement required soc side API to enable VMX support using CPU_COMMON
BUG=b:124518711
TEST= read msr 0x3a and verify vmx is enabled (value should be 5).
Change-Id: I33dbffa6301afabd688080751ba3b85a43e00156
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/amd/sr5650/pcie.c')
0 files changed, 0 insertions, 0 deletions