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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-05-11 22:53:19 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-05-19 14:46:58 +0200 |
commit | 017c2150d4a528c58a454705db74210477623a5f (patch) | |
tree | d26524851cb6d57a48dc951e1a160904edc995d6 /src/southbridge/amd/sr5650/cmn.h | |
parent | 58d5e21851ced6b475a87e3a4114b2c7e1125921 (diff) |
pcengines/apu1: Add switch between UART and GPIO modes
These are alternative customer options connected to J19 header.
We need to avoid modifying devicetree.cb, so we fix devicetree
for the super-io device-enables at runtime instead.
Change-Id: I04a79974b9bdf52b09ffc1b1362e201eab1ee011
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/sr5650/cmn.h')
0 files changed, 0 insertions, 0 deletions