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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-01 13:43:02 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-01 20:32:15 +0000 |
commit | f1b58b78351d7ed220673e688a2f7bc9e96da4e2 (patch) | |
tree | d8aae223f0e426f189cb4750b972a31e09d46b88 /src/southbridge/amd/sr5650/cmn.h | |
parent | 44e89af6e609874f2f18d30f1e66dce8b5a98eff (diff) |
device/pci: Fix PCI accessor headers
PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/amd/sr5650/cmn.h')
-rw-r--r-- | src/southbridge/amd/sr5650/cmn.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index 126b786246..30aeed25d6 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -18,6 +18,7 @@ #define __SR5650_CMN_H__ #include <arch/io.h> +#include <device/pci_ops.h> #define NBMISC_INDEX 0x60 #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ |