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| author | Subrata Banik <subrata.banik@intel.com> | 2018-11-20 13:20:31 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-11-22 02:26:33 +0000 |
| commit | 26d706bb333827c983abf7d734ce5af621d7adeb (patch) | |
| tree | 186347a0a9e64b0e0b2b474f8fe5148b856ce417 /src/southbridge/amd/sr5650/cmn.h | |
| parent | dd4ef173f1082f670ad6302bf93d37cc57f8b043 (diff) | |
soc/intel/icelake: Create macros for FSP consumption
1. Modify PCIEXBAR to accomodate Type-C Root Port
2. LPSS device mode selection
Change-Id: Ib7e4bc304f93e4b63ac2d7f194ca441dd96dd943
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29697
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/sr5650/cmn.h')
0 files changed, 0 insertions, 0 deletions