diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-12-06 15:05:19 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-19 05:30:23 +0000 |
| commit | ba8202948ab77bdbd3dc2197f1552b87791a659a (patch) | |
| tree | 0ccd235ac9809e6e50f043c7a659ba34e69fd69c /src/southbridge/amd/sr5650/chip.h | |
| parent | fd02ff0375d72b7e50d697446c877c3c8ad94efc (diff) | |
soc/intel/cannonlake: Declare SATA Mode clear
FSP support two SATA modes as AHCI mode (0) and RAID mode (1), make it
more clear in header file.
Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30093
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/sr5650/chip.h')
0 files changed, 0 insertions, 0 deletions