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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-11-21 11:08:04 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-11-23 06:16:06 +0000 |
| commit | 2fd2923aebae63bdf4567f70d933831f44e082ed (patch) | |
| tree | 8544928c3f80b22d9477ad2cf0d0c609cbf5b56e /src/southbridge/amd/sr5650/chip.h | |
| parent | bbf1df76a6eddbb91a425be9afda1cbf8a903a8d (diff) | |
mb/intel/icelake_rvp: Configure eSPI IO decode range for EC
This implementation adds eSPI IO decode range for EC.
1. 0x800-0x8FF / 0x200-020F: EC host command range.
2. 0x900-0x9ff: EC memory map range.
Change-Id: I69e6b3a83c072036c5b3ae801f8d80dfda82478e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/southbridge/amd/sr5650/chip.h')
0 files changed, 0 insertions, 0 deletions