Add AMD SR56x0 support.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 34 insertions, 0 deletions

diff --git a/src/southbridge/amd/sr5650/chip.h b/src/southbridge/amd/sr5650/chip.h
new file mode 100644
index 0000000000..43f8dd343c
--- /dev/null
+++ b/src/southbridge/amd/sr5650/chip.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SR5650_CHIP_H
+#define SR5650_CHIP_H
+
+/* Member variables are defined in Config.lb. */
+struct southbridge_amd_sr5650_config
+{
+	u8 gpp1_configuration;		/* The configuration of General Purpose Port. */
+	u8 gpp2_configuration;		/* The configuration of General Purpose Port. */
+	u8 gpp3a_configuration;		/* The configuration of General Purpose Port. */
+	u16 port_enable;		/* Which port is enabled? GPP(2,3,4,5,6,7,9,10,11,12,13) */
+};
+struct chip_operations;
+extern struct chip_operations southbridge_amd_sr5650_ops;
+
+#endif /* SR5650_CHIP_H */