diff options
| author | Duncan Laurie <dlaurie@google.com> | 2019-03-27 19:28:17 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-03-28 19:17:43 +0000 |
| commit | 31354676d05ac5992745d943f94d0dbc550ed95c (patch) | |
| tree | 545d4262f63cdfd19864c427f7aee206b84ecef8 /src/southbridge/amd/sb800/fadt.c | |
| parent | 13f5360724e9e6e5ede09487670f2c1a2ba86d41 (diff) | |
ec/google/wilco: Add a romstage init function to send progress code
When using FSP with debug enabled it takes too long to get to ramstage
and send the first progress code to the EC. The same thing has been
reported to happen when 2x16GB memory is installed.
BUG=b:127875364
TEST=boot with FSP debug and ensure EC does not try to turn off the
system while it is still booting.
Change-Id: I5676354f5e53540273a9029411507f91864735a1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/amd/sb800/fadt.c')
0 files changed, 0 insertions, 0 deletions