diff options
| author | efdesign98 <efdesign98@gmail.com> | 2011-07-20 12:37:58 -0600 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-07-22 00:20:59 +0200 |
| commit | 00c8c4a31632150fa711493f39e727da950ebe9f (patch) | |
| tree | f3bad2e78ddb6999ad551a73f05c049a266a14ab /src/southbridge/amd/sb700/smbus.h | |
| parent | 09ea8ea1a74d56a37755cec52077555b91f9e5b4 (diff) | |
Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/southbridge/amd/sb700/smbus.h')
| -rwxr-xr-x[-rw-r--r--] | src/southbridge/amd/sb700/smbus.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/southbridge/amd/sb700/smbus.h b/src/southbridge/amd/sb700/smbus.h index c21a1dc0a2..9ddfc35303 100644..100755 --- a/src/southbridge/amd/sb700/smbus.h +++ b/src/southbridge/amd/sb700/smbus.h @@ -20,6 +20,13 @@ #ifndef SB700_SMBUS_H #define SB700_SMBUS_H +#include <stdint.h> +#include "stddef.h" +#include <arch/io.h> + +#define SMBUS_IO_BASE 0x6000 /* Is it a temporary SMBus I/O base address? */ + /*SIZE 0x40 */ + #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1 #define SMBHSTCTRL 0x2 @@ -56,10 +63,11 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val); int do_smbus_recv_byte(u32 smbus_io_base, u32 device); int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); - #endif |