Update AMD SR5650 and SB700

This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes.  The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements.  This particular change
affects all mainboards that use the SB700, and their changes are
include herein.  These mainboards are:
  Advansus a785e,
  AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
  Asrock 939a785gmh,
  Asus m4a78-em, m4a785-m,
  Gigabyte ma785gm,
  Iei Kino-780am2-fam10
  Jetway pa78vm5
  Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.

Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>

1 files changed, 45 insertions, 44 deletions

diff --git a/src/southbridge/amd/sb700/smbus.c b/src/southbridge/amd/sb700/smbus.c
index e47bceed47..6edc3de80c 100644..100755
--- a/src/southbridge/amd/sb700/smbus.c
+++ b/src/southbridge/amd/sb700/smbus.c
@@ -22,6 +22,51 @@
 
 #include "smbus.h"
 
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
+	tmp = inl(AB_DATA);
+	/* rpr 4.2
+	 * For certain revisions of the chip, the ABCFG registers,
+	 * with an address of 0x100NN (where 'N' is any hexadecimal
+	 * number), require an extra programming step.*/
+	reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
+	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl(tmp, AB_DATA);
+	reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
+}
+
+/* space = 0: AX_INDXC, AX_DATAC
+ * space = 1: AX_INDXP, AX_DATAP
+ */
+void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	/* read axindc to tmp */
+	outl(space << 30 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(space << 30 | space << 3 | 0x34, AB_INDX);
+	tmp = inl(AB_DATA);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	/* write tmp */
+	outl(space << 30 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(space << 30 | space << 3 | 0x34, AB_INDX);
+	outl(tmp, AB_DATA);
+}
+
+
 static inline void smbus_delay(void)
 {
 	outb(inb(0x80), 0x80);
@@ -177,48 +222,4 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
 	return 0;
 }
 
-static void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
-{
-	u32 tmp;
-
-	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
-	tmp = inl(AB_DATA);
-	/* rpr 4.2
-	 * For certain revisions of the chip, the ABCFG registers,
-	 * with an address of 0x100NN (where 'N' is any hexadecimal
-	 * number), require an extra programming step.*/
-	reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
-	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
-	outl(tmp, AB_DATA);
-	reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
-}
-
-/* space = 0: AX_INDXC, AX_DATAC
- * space = 1: AX_INDXP, AX_DATAP
- */
-static inline void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
-			  u32 mask, u32 val)
-{
-	u32 tmp;
-
-	/* read axindc to tmp */
-	outl(space << 30 | space << 3 | 0x30, AB_INDX);
-	outl(axindc, AB_DATA);
-	outl(space << 30 | space << 3 | 0x34, AB_INDX);
-	tmp = inl(AB_DATA);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	/* write tmp */
-	outl(space << 30 | space << 3 | 0x30, AB_INDX);
-	outl(axindc, AB_DATA);
-	outl(space << 30 | space << 3 | 0x34, AB_INDX);
-	outl(tmp, AB_DATA);
-}
 #endif