diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-10-23 22:28:26 -0500 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2015-10-25 05:05:46 +0100 |
| commit | ee3ec8e21256e544ef0a32f283a65c0c47040948 (patch) | |
| tree | e15929b289e4a4e9876f217223cf7e53415285e3 /src/southbridge/amd/sb700/sm.c | |
| parent | 2a16acee6b5fe7c8007f29e6015e0eef443a9344 (diff) | |
southbridge/amd/sb700: Set up uninitialized devices in early boot
LPC decodes were not enabled, leading to a failure of POST 80 cards
and similar debugging devices. Enable the relevant LPC decodes
to allow debugging.
Additionally, the SMBUS controllers were not properly set up.
Enable both the primary and auxiliary controllers.
Finally, K10 and higher CPUs were hanging during boot due to
a misconfigued IOAPIC. Properly configure the IOAPIC.
Change-Id: I9ffb6542ce445ac971fb81f4f554e7f1313e6a98
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12177
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/amd/sb700/sm.c')
| -rw-r--r-- | src/southbridge/amd/sb700/sm.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 16958a2620..83a722bcb2 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -62,11 +62,9 @@ static void sm_init(device_t dev) printk(BIOS_INFO, "sm_init().\n"); rev = get_sb700_revision(dev); - ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0)); /* some like mem resource, but does not have enable bit */ - /* Don't rename APIC ID */ - /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8. - * We need to check out why and change back. */ - clear_ioapic(ioapic_base); + /* This works in a similar fashion to a memory resource, but without an enable bit */ + ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0)); + setup_ioapic(ioapic_base, 0); /* Don't rename IOAPIC ID. */ /* 2.10 Interrupt Routing/Filtering */ dword = pci_read_config8(dev, 0x62); @@ -298,6 +296,10 @@ static void sm_init(device_t dev) byte &= ~(1 << 1); pm_iowrite(0x59, byte); + /* Enable SCI as irq9. */ + outb(0x4, 0xC00); + outb(0x9, 0xC01); + printk(BIOS_INFO, "sm_init() end\n"); /* Enable NbSb virtual channel */ @@ -388,7 +390,7 @@ static void sb700_sm_read_resources(device_t dev) struct resource *res; /* Get the normal pci resources of this device */ - /* pci_dev_read_resources(dev); */ + pci_dev_read_resources(dev); /* apic */ res = new_resource(dev, 0x74); |