diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-08 19:35:06 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-11-11 18:45:14 +0100 |
| commit | 83abd81c8acb3a53dfc125e248d9e5fd58f3e0f7 (patch) | |
| tree | ca0652a1421652f4eb8b4af358f66e2fc256e1db /src/southbridge/amd/sb700/early_setup.c | |
| parent | dd4390b6e055ef862084a5fc45b756d6fe09151d (diff) | |
cpu/amd: Add CC6 support
This patch adds CC6 power save support to the AMD Family 15h
support code. As CC6 is a complex power saving state that
relies heavily on CPU, northbridge, and southbridge cooperation,
this patch alters significant amounts of code throughout the
tree simultaneously.
Allowing the CPU to enter CC6 allows the second level of turbo
boost to be reached, and also provides significant power savings
when the system is idle due to the complete core shutdown.
Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11979
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/amd/sb700/early_setup.c')
| -rw-r--r-- | src/southbridge/amd/sb700/early_setup.c | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 57fda78077..f109896ea3 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -268,10 +268,6 @@ void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) byte &= ~(1<<6); pmio_write(0x8d, byte); - byte = pmio_read(0x61); - byte &= ~0x04; - pmio_write(0x61, byte); - byte = pmio_read(0x42); byte &= ~0x04; pmio_write(0x42, byte); @@ -583,6 +579,13 @@ static void sb700_devices_por_init(void) static void sb700_pmio_por_init(void) { u8 byte; + uint8_t enable_c_states; + + enable_c_states = 0; +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + if (get_option(&byte, "cpu_c_states") == CB_SUCCESS) + enable_c_states = !!byte; +#endif printk(BIOS_INFO, "sb700_pmio_por_init()\n"); /* K8KbRstEn, KB_RST# control for K8 system. */ @@ -644,6 +647,14 @@ static void sb700_pmio_por_init(void) byte |= 1 << 0; pmio_write(0xB2, byte); + /* Set up IOAPIC and BM_STS monitoring */ + byte = pmio_read(0x61); + if (enable_c_states) + byte |= 0x4; + else + byte &= ~0x04; + pmio_write(0x61, byte); + /* NOTE: Enabling automatic C1e state switch caused failures when initializing processors */ /* Enable precision HPET clock and automatic C state switch */ |