Merge enable_rom.c files into bootblock.c files.

All southbridges using TINY_BOOTBLOCK have a bootblock.c files which
simply includes an enable_rom.c files. As discussed on the mailing
list, drop the enable_rom.c file by merging it into bootblock.c.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 48 insertions, 69 deletions

diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c
index a5eb2f2fac..70076227bf 100644
--- a/src/southbridge/amd/sb600/bootblock.c
+++ b/src/southbridge/amd/sb600/bootblock.c
@@ -1,12 +1,11 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * the Free Software Foundation; version 2 of the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -18,7 +17,52 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "southbridge/amd/sb600/enable_rom.c"
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+/*
+ * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
+ *
+ * Hardware should enable LPC ROM by pin straps. This function does not
+ * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
+ *
+ * The SB600 power-on default is to map 256K ROM space.
+ *
+ * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15.
+ */
+static void sb600_enable_rom(void)
+{
+	u8 reg8;
+	device_t dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
+				       PCI_DEVICE_ID_ATI_SB600_LPC), 0);
+
+	/* Decode variable LPC ROM address ranges 1 and 2. */
+	reg8 = pci_read_config8(dev, 0x48);
+	reg8 |= (1 << 3) | (1 << 4);
+	pci_write_config8(dev, 0x48, reg8);
+
+	/* LPC ROM address range 1: */
+	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
+	pci_write_config16(dev, 0x68, 0x000e);
+	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
+	pci_write_config16(dev, 0x6a, 0x000f);
+
+	/* LPC ROM address range 2: */
+	/*
+	 * Enable LPC ROM range start at:
+	 * 0xfff8(0000): 512KB
+	 * 0xfff0(0000): 1MB
+	 * 0xffe0(0000): 2MB
+	 * 0xffc0(0000): 4MB
+	 */
+	pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
+	/* Enable LPC ROM range end at 0xffff(ffff). */
+	pci_write_config16(dev, 0x6e, 0xffff);
+}
 
 static void bootblock_southbridge_init(void)
 {
diff --git a/src/southbridge/amd/sb600/enable_rom.c b/src/southbridge/amd/sb600/enable_rom.c
deleted file mode 100644
index b2668420ce..0000000000
--- a/src/southbridge/amd/sb600/enable_rom.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_ids.h>
-
-/*
- * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
- *
- * Hardware should enable LPC ROM by pin straps. This function does not
- * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
- *
- * The SB600 power-on default is to map 256K ROM space.
- *
- * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15.
- */
-static void sb600_enable_rom(void)
-{
-	u8 reg8;
-	device_t dev;
-
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
-				       PCI_DEVICE_ID_ATI_SB600_LPC), 0);
-
-	/* Decode variable LPC ROM address ranges 1 and 2. */
-	reg8 = pci_read_config8(dev, 0x48);
-	reg8 |= (1 << 3) | (1 << 4);
-	pci_write_config8(dev, 0x48, reg8);
-
-	/* LPC ROM address range 1: */
-	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
-	pci_write_config16(dev, 0x68, 0x000e);
-	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
-	pci_write_config16(dev, 0x6a, 0x000f);
-
-	/* LPC ROM address range 2: */
-	/*
-	 * Enable LPC ROM range start at:
-	 * 0xfff8(0000): 512KB
-	 * 0xfff0(0000): 1MB
-	 * 0xffe0(0000): 2MB
-	 * 0xffc0(0000): 4MB
-	 */
-	pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
-	/* Enable LPC ROM range end at 0xffff(ffff). */
-	pci_write_config16(dev, 0x6e, 0xffff);
-}