diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-08-12 20:40:37 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-08-29 18:35:47 +0200 |
| commit | 24100100181bd770ce0f1181a1770a0808790cde (patch) | |
| tree | ed9b812999f747902f0294859f98b149848716f9 /src/southbridge/amd/sb600 | |
| parent | f7381f8cd1cf4307dcccd5728fc11afce3610439 (diff) | |
usbdebug: Change debug port scanning
On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan
all physical ports one after other in incrementing order. To avoid
possible problems with other USB devices, one can select the port
number here and bypass the scan.
Intel platforms can communicate with usbdebug dongle on one
physical port only, and this option makes no difference there.
Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3872
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge/amd/sb600')
| -rw-r--r-- | src/southbridge/amd/sb600/Kconfig | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/enable_usbdebug.c | 3 |
2 files changed, 0 insertions, 7 deletions
diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 4ae4641b86..fe9468d4af 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -36,10 +36,6 @@ config EHCI_DEBUG_OFFSET hex default 0xe0 -config USBDEBUG_DEFAULT_PORT - int - default 0 - choice prompt "SATA Mode" default SATA_MODE_IDE diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index d20c8c4fe1..40c53aecfa 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -36,9 +36,6 @@ void enable_usbdebug(unsigned int port) { pci_devfn_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ - /* Select the requested physical USB port (1-15) as the Debug Port. */ - set_debug_port(port); - /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); |