diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-01-16 17:53:38 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-01-16 17:53:38 +0000 |
| commit | 9fe4d797a37671a65053add3f7cca27397db0b9b (patch) | |
| tree | 5cabbdc8b6e7eb970891b55d1ea3727a4a71aca2 /src/southbridge/amd/sb600/sb600_usb.c | |
| parent | 984e0f3a0c3a82339ef8afcf7f315f377e0c81fc (diff) | |
coreboot used to have two different "APIs" for memory accesses:
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)
read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.
This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/sb600/sb600_usb.c')
| -rw-r--r-- | src/southbridge/amd/sb600/sb600_usb.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/amd/sb600/sb600_usb.c b/src/southbridge/amd/sb600/sb600_usb.c index 2002114f81..4be2d73272 100644 --- a/src/southbridge/amd/sb600/sb600_usb.c +++ b/src/southbridge/amd/sb600/sb600_usb.c @@ -98,16 +98,16 @@ static void usb_init2(struct device *dev) /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; - writel(dword, usb2_bar0 + 0xC0); + write32(usb2_bar0 + 0xC0, dword); /* RPR5.5 Sets In/OUT FIFO threshold for best performance */ dword = 0x00200040; - writel(dword, usb2_bar0 + 0xA4); + write32(usb2_bar0 + 0xA4, dword); /* RPR5.9 Disable the EHCI Dynamic Power Saving feature */ - word = readl(usb2_bar0 + 0xBC); + word = read16(usb2_bar0 + 0xBC); word &= ~(1 << 12); - writew(word, usb2_bar0 + 0xBC); + write16(usb2_bar0 + 0xBC, word); /* RPR5.10 Disable EHCI MSI support */ byte = pci_read_config8(dev, 0x50); |