diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-01-16 17:53:38 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-01-16 17:53:38 +0000 |
commit | 9fe4d797a37671a65053add3f7cca27397db0b9b (patch) | |
tree | 5cabbdc8b6e7eb970891b55d1ea3727a4a71aca2 /src/southbridge/amd/sb600/sb600_sata.c | |
parent | 984e0f3a0c3a82339ef8afcf7f315f377e0c81fc (diff) |
coreboot used to have two different "APIs" for memory accesses:
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)
read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.
This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/sb600/sb600_sata.c')
-rw-r--r-- | src/southbridge/amd/sb600/sb600_sata.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/amd/sb600/sb600_sata.c b/src/southbridge/amd/sb600/sb600_sata.c index 3d7f2c416c..b0074b70e3 100644 --- a/src/southbridge/amd/sb600/sb600_sata.c +++ b/src/southbridge/amd/sb600/sb600_sata.c @@ -172,7 +172,7 @@ static void sata_init(struct device *dev) /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ for (i = 0; i < 4; i++) { - byte = readb(sata_bar5 + 0x128 + 0x80 * i); + byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk_spew("SATA port %i status = %x\n", i, byte); byte &= 0xF; @@ -182,24 +182,24 @@ static void sata_init(struct device *dev) printk_spew("SATA device detected but not talking. Trying lower speed.\n"); /* Read in Port-N Serial ATA Control Register */ - byte = readb(sata_bar5 + 0x12C + 0x80 * i); + byte = read8(sata_bar5 + 0x12C + 0x80 * i); /* Set Reset Bit and 1.5g bit */ byte |= 0x11; - writeb(byte, (sata_bar5 + 0x12C + 0x80 * i)); + write8((sata_bar5 + 0x12C + 0x80 * i), byte); /* Wait 1ms */ mdelay(1); /* Clear Reset Bit */ byte &= ~0x01; - writeb(byte, (sata_bar5 + 0x12C + 0x80 * i)); + write8((sata_bar5 + 0x12C + 0x80 * i), byte); /* Wait 1ms */ mdelay(1); /* Reread status */ - byte = readb(sata_bar5 + 0x128 + 0x80 * i); + byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk_spew("SATA port %i status = %x\n", i, byte); byte &= 0xF; } @@ -223,15 +223,15 @@ static void sata_init(struct device *dev) /* Below is CIM InitSataLateFar */ /* Enable interrupts from the HBA */ - byte = readb(sata_bar5 + 0x4); + byte = read8(sata_bar5 + 0x4); byte |= 1 << 1; - writeb(byte, (sata_bar5 + 0x4)); + write8((sata_bar5 + 0x4), byte); /* Clear error status */ - writel(0xFFFFFFFF, (sata_bar5 + 0x130)); - writel(0xFFFFFFFF, (sata_bar5 + 0x1b0)); - writel(0xFFFFFFFF, (sata_bar5 + 0x230)); - writel(0xFFFFFFFF, (sata_bar5 + 0x2b0)); + write32((sata_bar5 + 0x130), 0xFFFFFFFF); + write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); + write32((sata_bar5 + 0x230), 0xFFFFFFFF); + write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */ /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */ @@ -241,7 +241,7 @@ static void sata_init(struct device *dev) /* byte = pm_ioread(0x29); */ /* word |= byte<<8; */ /* printk_debug("AcpiGpe0Blk addr = %x\n", word); */ - /* writel(0x80000000 , word); */ + /* write32(word, 0x80000000); */ } static struct pci_operations lops_pci = { |