diff options
author | Michael Xie <Michael.Xie@amd.com> | 2008-09-22 13:11:39 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2008-09-22 13:11:39 +0000 |
commit | 7586cef37aace94f1558a391b25245f08523ab95 (patch) | |
tree | 92dd060f73e441bd702b26bb04231d4be9d0ecc1 /src/southbridge/amd/sb600/sb600_reset.c | |
parent | 06755e404eb4b97dab5bc5ff90443f7d7d74d3cf (diff) |
Patch for AMD SB600 chipset.
Most of the functions in SB600 are enabled except power management.
Signed-off-by: Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/sb600/sb600_reset.c')
-rw-r--r-- | src/southbridge/amd/sb600/sb600_reset.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/southbridge/amd/sb600/sb600_reset.c b/src/southbridge/amd/sb600/sb600_reset.c new file mode 100644 index 0000000000..d46f734c3d --- /dev/null +++ b/src/southbridge/amd/sb600/sb600_reset.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> + +#define PCI_DEV(BUS, DEV, FN) ( \ + (((BUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x7) << 12)) + +typedef unsigned device_t; + +#include "../../../northbridge/amd/amdk8/reset_test.c" + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} |