diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-12-16 20:52:23 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-17 17:03:08 +0100 |
| commit | a9e3a756fe7a68c1839dd5a33b3aa03ca1224327 (patch) | |
| tree | bcac8ba7e7d415493b9fe6265518f7eee1da74d6 /src/southbridge/amd/rs780/rs780.h | |
| parent | 3c3a50c3c4144a393b4183d4e57ae9c7c2d8cc53 (diff) | |
southbridge/amd rs690 & rs780 spelling fixes
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: I5a5af71ea49152accd92dc331a19e57f3717e4ff
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7841
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/amd/rs780/rs780.h')
| -rw-r--r-- | src/southbridge/amd/rs780/rs780.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index c44a81347b..f84604df58 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -78,7 +78,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 ULONG ulSystemConfig; //[0]=1: PowerExpress mode // =0 Non-PowerExpress mode; -//[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will disable other power state in VBIOS table. +//[1]=1: system boots up at AMD overdriven state or user customized mode. In this case, driver will disable other power state in VBIOS table. // =0: system boots up at driver control state. Power state depends on VBIOS PP table. //[2]=1: PWM method is used on NB voltage control. // =0: GPIO method is used. @@ -90,7 +90,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 // =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. //[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and VBIOS PP table voltage drop/throttling request will be ignored. // =0: Voltage settings is determined by VBIOS PP table. -//[7]=1: Enable CLMC Hybird Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. +//[7]=1: Enable CLMC Hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. // =0: Enable regular CLMC mode, CDLD and CILR will be enabled. //[8]=1: CDLF is supported and enabled by fuse //CHP 914 // =0: CDLF is not supported and not enabled by fuses @@ -174,7 +174,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 * ------------------------------------------------- */ extern PCIE_CFG AtiPcieCfg; -/* ----------------- export funtions ----------------- */ +/* ----------------- export functions ----------------- */ u32 nbmisc_read_index(device_t nb_dev, u32 index); void nbmisc_write_index(device_t nb_dev, u32 index, u32 data); u32 nbpcie_p_read_index(device_t dev, u32 index); |