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authorhuang lin <hl@rock-chips.com>2016-03-03 15:29:34 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-04-05 13:34:47 +0200
commit7b9bca0b2b1830262daffd16f285e868d241391b (patch)
treec89de1ccd13adc983d2cb5aaef1fefbe4483632e /src/southbridge/amd/rs780/pcie.c
parent473e0c35fe2ecd70ed791936e65d8924f16e528c (diff)
libpayload: mmu: Initialize the base 4GiB as device memory
This allows to accommodate different platforms' default configurations, memory configuration is fine tuned later during boot process. BUG=chrome-os-partner:51537 BRANCH=none TEST=none yet, the full stack of patches boots fine on EVB Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 97a9a71ade4df8a501043f9ae58463a3135e2a4f Original-Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332384 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/13914 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/amd/rs780/pcie.c')
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