diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-03 06:12:03 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 08:46:56 +0000 |
| commit | 564c2191ab5d2c57ce7d3fda9a7596ef3e39b975 (patch) | |
| tree | c21f844d42c7addb874ea83b060e45b785d5cdf5 /src/southbridge/amd/rs780/cmn.c | |
| parent | 1bad4ce421188748d1c3dd6bafe3863cbb21dd24 (diff) | |
sb/amd/rs780: Fix invalid function declarations
Provide empty stub implementations for set_pcie_reset() and
set_pcie_dereset(), many boards do not provide a proper one.
Change-Id: Ia6811442905ef1776fa5a8e3f5d4433e86e42f88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/rs780/cmn.c')
| -rw-r--r-- | src/southbridge/amd/rs780/cmn.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index c39c6e9968..b849e1efa7 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -256,9 +256,6 @@ u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port) u32 lc_state, reg, current_link_width, lane_mask; int8_t current, res = 0; u32 gfx_gpp_sb_sel; - void set_pcie_dereset(void); - void set_pcie_reset(void); - switch (port) { case 2 ... 3: gfx_gpp_sb_sel = PCIE_CORE_INDEX_GFX; @@ -397,3 +394,11 @@ int is_family10h(void) { return cpuidFamily() == 0x10; } + +__weak void set_pcie_reset(void) +{ +} + +__weak void set_pcie_dereset(void) +{ +} |