Features supported in RS780 code:

  * PCIe initialization.
  * Internal Graphics initialization.
  * HT Link initialization. It works in HT1 or HT3 mode.

Note:
1. I tried to add the description of every step to the code. For example,
   if it is made based on rpr, section 2.4.5, I will pasted the words
   from 2.4.5 to the c code. But the document I worked with might be
   different with the most updated one. A new section has been added and
   the 2.4.5 might be changed to 2.5.5. That migh lead to confusing. I
   correct every comment if I met one. But I have to confess that I am so
   reluctant to find out everyone. I believe it will be correct in the long
   run.
2. The interanl graphics part is done by Libo Feng <libo.feng@amd.com>.
3. There is a conflict between RPR and our CIM code. Please see the comment in
   switching_gppsb_configurations in rs780_pcie.c.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 40 insertions, 0 deletions

diff --git a/src/southbridge/amd/rs780/chip.h b/src/southbridge/amd/rs780/chip.h
new file mode 100644
index 0000000000..fa72a01e31
--- /dev/null
+++ b/src/southbridge/amd/rs780/chip.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef RS780_CHIP_H
+#define RS780_CHIP_H
+
+/* Member variables are defined in Config.lb. */
+struct southbridge_amd_rs780_config
+{
+	u8 gppsb_configuration;		/* The configuration of General Purpose Port, A/B/C/D/E. */
+	u8 gpp_configuration;		/* The configuration of General Purpose Port, C/D. */
+	u16 port_enable;		/* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
+	u8 gfx_dev2_dev3;		/* for GFX Core initialization REFCLK_SEL */
+	u8 gfx_dual_slot;		/* Is it dual graphics slots */
+	u8 gfx_lane_reversal;		/* Single/Dual slot lan reversal */
+	u8 gfx_tmds;			/* whether support TMDS? */
+	u8 gfx_compliance;		/* whether support compliance? */
+	u8 gfx_reconfiguration;		/* Dynamic Lind Width Control */
+	u8 gfx_link_width;		/* Desired width of lane 2 */
+};
+struct chip_operations;
+extern struct chip_operations southbridge_amd_rs780_ops;
+
+#endif /* RS780_CHIP_H */