southbridge/amd rs690 & rs780 spelling fixes

Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.

Change-Id: I5a5af71ea49152accd92dc331a19e57f3717e4ff
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7841
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

5 files changed, 11 insertions, 11 deletions

diff --git a/src/southbridge/amd/rs690/chip.h b/src/southbridge/amd/rs690/chip.h
index ec8aa05cb6..689a5dd8a2 100644
--- a/src/southbridge/amd/rs690/chip.h
+++ b/src/southbridge/amd/rs690/chip.h
@@ -30,7 +30,7 @@ struct southbridge_amd_rs690_config
 	u8 gfx_lane_reversal;	/* Single/Dual slot lan reversal */
 	u8 gfx_tmds;		/* whether support TMDS? */
 	u8 gfx_compliance;	/* whether support compliance? */
-	u8 gfx_reconfiguration;	/* Dynamic Lind Width Control */
+	u8 gfx_reconfiguration;	/* Dynamic Link Width Control */
 	u8 gfx_link_width;	/* Desired width of lane 2 */
 };
 
diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c
index 86a6976606..eba1c75b50 100644
--- a/src/southbridge/amd/rs690/cmn.c
+++ b/src/southbridge/amd/rs690/cmn.c
@@ -273,7 +273,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 			res = 0;
 			count = 0;
 			break;
-		case 0x07:	/* device is in compliance state (training sequence is doen). Move to train the next device */
+		case 0x07:	/* device is in compliance state (training sequence is done). Move to train the next device */
 			res = 1;	/* TODO: CIM sets it to 0 */
 			count = 0;
 			break;
diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c
index 42e6c35020..4de5aca608 100644
--- a/src/southbridge/amd/rs690/gfx.c
+++ b/src/southbridge/amd/rs690/gfx.c
@@ -19,7 +19,7 @@
 
 /*
  *  for rs690 internal graphics device
- *  device id of internal grphics:
+ *  device id of internal graphics:
  *	RS690M/T: 0x791f
  *    RS690:	   0x791e
  */
@@ -509,7 +509,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
         printk(BIOS_INFO, "rs690_gfx_init step6.\n");
 
 	/* step 7 compliance state, (only need if CMOS option is enabled) */
-	/* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
+	/* the compliance state is just for test. refer to 4.2.5.2 of PCIe specification */
 	if (cfg->gfx_compliance) {
 		/* force compliance */
 		set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6);
@@ -558,7 +558,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 	pci_write_config16(dev, 0x5a, reg16);
 	printk(BIOS_INFO, "rs690_gfx_init step8.9.\n");
 
-	/* step 8.10 Setting this register to 0x1 will hide the Advanced Error Rporting Capabilities in the PCIE Brider.
+	/* step 8.10 Setting this register to 0x1 will hide the Advanced Error Reporting Capabilities in the PCIE Bridge.
 	 * This will workaround several failures reported by the PCI Compliance test under Vista DTM. */
 	set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 31, 0 << 31);
 	printk(BIOS_INFO, "rs690_gfx_init step8.10.\n");
diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c
index 0bd4da5735..d2817255e0 100644
--- a/src/southbridge/amd/rs690/pcie.c
+++ b/src/southbridge/amd/rs690/pcie.c
@@ -142,7 +142,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
 	reg |= cfg->gpp_configuration << 4;
 	nbmisc_write_index(nb_dev, 0x67, reg);
 
-	/* read bit14 and write back its inverst value */
+	/* read bit14 and write back its inverted value */
 	reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
 	reg ^= RECONFIG_GPPSB_GPPSB;
 	nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
@@ -256,7 +256,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 	case 7:
 		/* Blocks DMA traffic during C3 state */
 		set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
-		/* Enabels TLP flushing */
+		/* Enables TLP flushing */
 		set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
 
 		/* check port enable */
@@ -301,10 +301,10 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 	}
 
 	/* step 6b: L0s for the southbridge link */
-	/* To enalbe L0s in the southbridage*/
+	/* To enable L0s in the southbridge*/
 
 	/* step 6c: L0s for the GPP link(s) */
-	/* To eable L0s in the RS690 for the GPP port(s) */
+	/* To enable L0s in the RS690 for the GPP port(s) */
 	set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
 	set_pcie_enable_bits(dev, 0xa0, 0xf << 8, 0x9 << 8);
 	reg16 = pci_read_config16(dev, 0x68);
@@ -312,7 +312,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 	pci_write_config16(dev, 0x68, reg16);
 
 	/* step 6d: ASPM L1 for the southbridge link */
-	/* To enalbe L1s in the southbridage*/
+	/* To enable L1s in the southbridge*/
 
 	/* step 6e: ASPM L1 for GPP link(s) */;
 	set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
diff --git a/src/southbridge/amd/rs690/rs690.h b/src/southbridge/amd/rs690/rs690.h
index 9f143d4b22..5bad41e4e1 100644
--- a/src/southbridge/amd/rs690/rs690.h
+++ b/src/southbridge/amd/rs690/rs690.h
@@ -104,7 +104,7 @@ typedef enum _NB_REVISION_ {
 * ------------------------------------------------- */
 extern PCIE_CFG AtiPcieCfg;
 
-/* ----------------- export funtions ----------------- */
+/* ----------------- export functions ----------------- */
 u32 nbmisc_read_index(device_t nb_dev, u32 index);
 void nbmisc_write_index(device_t nb_dev, u32 index, u32 data);
 u32 nbpcie_p_read_index(device_t dev, u32 index);