diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-31 19:22:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:22:46 +0200 |
| commit | ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 (patch) | |
| tree | 9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f /src/southbridge/amd/rs690/pcie.c | |
| parent | 2e4d80687dd79890c7c9edad8dbaf6e89edf2afc (diff) | |
src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/amd/rs690/pcie.c')
| -rw-r--r-- | src/southbridge/amd/rs690/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index bcf4f4d554..043c2eef5c 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -84,7 +84,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port) PCIE_GFX_COMPLIANCE))) { } - if (!cfg->gfx_tmds){ + if (!cfg->gfx_tmds){ /* step 3 Power Down Control for Southbridge */ reg = nbpcie_p_read_index(dev, 0xa2); |