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| author | Martin Roth <martin.roth@se-eng.com> | 2014-12-16 20:52:23 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-17 17:03:08 +0100 |
| commit | a9e3a756fe7a68c1839dd5a33b3aa03ca1224327 (patch) | |
| tree | bcac8ba7e7d415493b9fe6265518f7eee1da74d6 /src/southbridge/amd/rs690/cmn.c | |
| parent | 3c3a50c3c4144a393b4183d4e57ae9c7c2d8cc53 (diff) | |
southbridge/amd rs690 & rs780 spelling fixes
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: I5a5af71ea49152accd92dc331a19e57f3717e4ff
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7841
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/amd/rs690/cmn.c')
| -rw-r--r-- | src/southbridge/amd/rs690/cmn.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 86a6976606..eba1c75b50 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -273,7 +273,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) res = 0; count = 0; break; - case 0x07: /* device is in compliance state (training sequence is doen). Move to train the next device */ + case 0x07: /* device is in compliance state (training sequence is done). Move to train the next device */ res = 1; /* TODO: CIM sets it to 0 */ count = 0; break; |