diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-04-10 17:03:32 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-04-26 10:53:16 +0000 |
| commit | e742b68f1ac9324ce1f700323f1226e86d068a8c (patch) | |
| tree | b7fc74a0d5a1d6b3ba0773b59839d2bc15fddcb0 /src/southbridge/amd/pi | |
| parent | ae1b2d49cf0ad09ff8f1e3904a9e7b23d6fb423b (diff) | |
arch/x86/ioapic: Promote ioapic_get_sci_pin()
Platform needs to implement this to provide information about SCI IRQ
pin and polarity, to be used for filling in ACPI FADT and MADT entries.
Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/amd/pi')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/fadt.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/hudson.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/sm.c | 7 |
3 files changed, 9 insertions, 2 deletions
diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 1865d36b2c..fe65fb23da 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -25,8 +25,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { printk(BIOS_DEBUG, "pm_base: 0x%04x\n", HUDSON_ACPI_IO_BASE); - fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ - if (permanent_smi_handler()) { fadt->smi_cmd = ACPI_SMI_CTL_PORT; fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index e202824936..231766b472 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -42,6 +42,8 @@ #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ +#define ACPI_SCI_IRQ 9 + #define ACPI_SMI_CTL_PORT 0xb2 #define ACPI_SMI_CMD_CST_CONTROL 0xde #define ACPI_SMI_CMD_PST_CONTROL 0xad diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 2dc2ae3924..593f54805d 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -19,6 +19,13 @@ * HUDSON enables SATA by default in SMBUS Control. */ +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) +{ + *gsi = ACPI_SCI_IRQ; + *irq = ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW; +} + static void sm_init(struct device *dev) { register_new_ioapic_gsi0(VIO_APIC_VADDR); |