sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37168
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 67 insertions, 17 deletions

diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 0eccadb4f9..615fc048d6 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -28,7 +28,11 @@
 #
 #*****************************************************************************
 
-bootblock-y += enable_usbdebug.c
+ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
+bootblock-y += bootblock.c
+bootblock-y += early_setup.c
+bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+endif
 
 romstage-y += early_setup.c
 romstage-y += enable_usbdebug.c
diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c
index f12cec8602..e9a9d337c4 100644
--- a/src/southbridge/amd/pi/hudson/bootblock.c
+++ b/src/southbridge/amd/pi/hudson/bootblock.c
@@ -60,3 +60,50 @@ static void bootblock_southbridge_init(void)
 {
 	hudson_enable_rom();
 }
+
+#if !CONFIG(ROMCC_BOOTBLOCK)
+
+#include <bootblock_common.h>
+#include <amdblocks/acpimmio.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+
+void bootblock_soc_early_init(void)
+{
+	pci_devfn_t dev;
+	u32 data;
+
+	bootblock_southbridge_init();
+	hudson_lpc_decode();
+	if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON))
+		enable_acpimmio_decode_pm24();
+	else
+		enable_acpimmio_decode_pm04();
+
+	dev = PCI_DEV(0, 0x14, 3);
+	data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
+	/* enable 0x2e/0x4e IO decoding for SuperIO */
+	pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
+
+	/*
+	 * Enable FCH to decode TPM associated Memory and IO regions for vboot
+	 *
+	 * Enable decoding of TPM cycles defined in TPM 1.2 spec
+	 * Enable decoding of legacy TPM addresses: IO addresses 0x7f-
+	 * 0x7e and 0xef-0xee.
+	 */
+
+	data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE);
+	data |= TPM_12_EN | TPM_LEGACY_EN;
+	pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data);
+
+	/*
+	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+	 *  LpcClk[1:0]".  This following register setting has been
+	 *  replicated in every reference design since Parmer, so it is
+	 *  believed to be required even though it is not documented in
+	 *  the SoC BKDGs.  Without this setting, there is no serial
+	 *  output.
+	 */
+	pm_write8(0xd2, 0);
+}
+#endif
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 3453021a5e..56b894c852 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -123,22 +123,17 @@ void hudson_lpc_port80(void)
 void hudson_lpc_decode(void)
 {
 	pci_devfn_t dev;
-	u32 tmp = 0;
-
-	/* Enable I/O decode to LPC bus */
-	dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
-	tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
-		| DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0
-		| DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2
-		| DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4
-		| DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6
-		| DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0
-		| DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2
-		| DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2
-		| DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0
-		| DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT
-		| DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
-		| DECODE_ENABLE_ADLIB_PORT;
+	u32 tmp;
+
+	dev = PCI_DEV(0, 0x14, 3);
+	/* Serial port numeration on Hudson:
+	 * PORT0 - 0x3f8
+	 * PORT1 - 0x2f8
+	 * PORT5 - 0x2e8
+	 * PORT7 - 0x3e8
+	 */
+	tmp =  DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1
+	     | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7;
 
 	pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp);
 }
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index ac35536bc2..6264319dd4 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -117,6 +117,10 @@
 #define   LPC_ALT_WIDEIO1_ENABLE	BIT(2)
 #define   LPC_ALT_WIDEIO0_ENABLE	BIT(0)
 
+#define LPC_TRUSTED_PLATFORM_MODULE	0x7c
+#define   TPM_12_EN			BIT(0)
+#define   TPM_LEGACY_EN			BIT(2)
+
 #define LPC_WIDEIO2_GENERIC_PORT	0x90
 
 #define SPI_CNTRL0			0x00