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authorV Sowmya <v.sowmya@intel.com>2021-01-15 14:01:54 +0530
committerPatrick Georgi <pgeorgi@google.com>2021-02-06 09:09:16 +0000
commit1b150cb000a189f7564486ec9411222718374111 (patch)
treedadcd64d385230fe4ead39c3714bc2ae19d98457 /src/southbridge/amd/pi
parent72463720a2aa831c703e2536843f5f58ed32091d (diff)
mb/intel/shadowmountain: Add bootblock and verstage code
This patch includes the bootblock and verstage changes for shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early romstage. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/southbridge/amd/pi')
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