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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-07-13 12:06:25 -0600 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-24 11:40:43 +0000 |
| commit | 0bf3f55b5ce3cf4f75c28f6e4e2c2a711cd45535 (patch) | |
| tree | be6a7ea6fc6bc5db2112597affca371d48fe9a72 /src/southbridge/amd/pi | |
| parent | 9e741bb218aba8fde1e8967188b4588821aeb288 (diff) | |
amd/pi/hudson: Convert 48Mhz en to read/write32
Change-Id: I91e09757e5eea1eaf9b76921ad032ad2b79c14c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/amd/pi')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/early_setup.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index b5e753d222..ae8b406ad6 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -260,18 +260,17 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) void hudson_clk_output_48Mhz(void) { - u32 data, *memptr; + u32 ctrl; /* * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * 48Mhz will be on ball AP13 (FT3b package) */ - memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 ); - data = *memptr; + ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ - data &= (u32)~(1<<2); - *memptr = data; + ctrl &= (u32)~(1<<2); + write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); } static uintptr_t hudson_spibase(void) |