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authorMarc Jones <marcj303@gmail.com>2017-04-20 16:48:42 -0600
committerMarc Jones <marc@marcjonesconsulting.com>2017-04-26 04:14:12 +0200
commit6fcaaef6140aca68603f57d1c684c3381d472ac4 (patch)
tree3c642feacf9b7782d1232ffdd30843b491d46ec0 /src/southbridge/amd/pi/hudson/lpc.c
parentc1f32336e62c846073bdb0d92b54a84ac7320c3c (diff)
amd/pi/hudson: Add TPM decode to SPI function
Add a function to send the TPM decode to the SPI interface. Enables use of SPI TPMs on Hudson mainboards. Change-Id: I0e85ed92163e38eca6a55456708ab322d6a90d4c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19402 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/pi/hudson/lpc.c')
-rw-r--r--src/southbridge/amd/pi/hudson/lpc.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c
index d73979cd97..60a1b88bae 100644
--- a/src/southbridge/amd/pi/hudson/lpc.c
+++ b/src/southbridge/amd/pi/hudson/lpc.c
@@ -126,10 +126,13 @@ static void hudson_lpc_read_resources(device_t dev)
static void hudson_lpc_set_resources(struct device *dev)
{
struct resource *res;
+ u32 spi_enable_bits;
- /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
+ /* Special case. The SpiRomEnable and other enables should STAY set. */
res = find_resource(dev, 2);
- pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
+ spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
+ spi_enable_bits &= 0xF;
+ pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits);
pci_dev_set_resources(dev);
}