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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-12-01 17:41:23 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-05 17:01:48 +0000 |
| commit | 287ce5f1ee8c3765d05bfbc0a6dd5ea9ec8b5c87 (patch) | |
| tree | 9ffb1915bf2186e3a5f41af09f968d5b3ce1902a /src/southbridge/amd/pi/hudson/imc.c | |
| parent | d913036e18034d6756805aabd868e1091c97ac0c (diff) | |
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/amd/pi/hudson/imc.c')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/imc.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c index 6a01a764cb..3c6054d147 100644 --- a/src/southbridge/amd/pi/hudson/imc.c +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -16,6 +16,7 @@ #define __SIMPLE_DEVICE__ #include "imc.h" +#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/device.h> @@ -26,24 +27,24 @@ #include <Proc/Fch/Fch.h> #include <Proc/Fch/FchPlatform.h> -#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE) - void imc_reg_init(void) { u8 reg8; /* Init Power Management Block 2 (PM2) Registers. * Check BKDG for AMD Family 16h for details. */ - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x00), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x01), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x02), 0xf7); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x03), 0xff); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x04), 0xff); + /* Init Power Management Block 2 (PM2) Registers. + * Check BKDG for AMD Family 16h for details. */ + pm2_write8(0, 0x06); + pm2_write8(1, 0x06); + pm2_write8(2, 0xf7); + pm2_write8(3, 0xff); + pm2_write8(4, 0xff); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x10), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x11), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x12), 0xf7); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x13), 0xff); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x14), 0xff); + pm2_write8(0x10, 0x06); + pm2_write8(0x11, 0x06); + pm2_write8(0x12, 0xf7); + pm2_write8(0x13, 0xff); + pm2_write8(0x14, 0xff); reg8 = pci_read_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4); reg8 &= 0x8F; |