diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-11-23 18:03:46 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-04 16:39:33 +0000 |
| commit | 8cee45c3f8f05d936ba181f56405b8c936666a36 (patch) | |
| tree | 36e0cf79a1438e53b28ff51d0c6b5c9d7bd83cb8 /src/southbridge/amd/pi/hudson/bootblock.c | |
| parent | 55009af42c39f413c49503670ce9bc2858974962 (diff) | |
sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37168
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/pi/hudson/bootblock.c')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/bootblock.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index f12cec8602..e9a9d337c4 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -60,3 +60,50 @@ static void bootblock_southbridge_init(void) { hudson_enable_rom(); } + +#if !CONFIG(ROMCC_BOOTBLOCK) + +#include <bootblock_common.h> +#include <amdblocks/acpimmio.h> +#include <southbridge/amd/pi/hudson/hudson.h> + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) + enable_acpimmio_decode_pm24(); + else + enable_acpimmio_decode_pm04(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + pm_write8(0xd2, 0); +} +#endif |