diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/pi/hudson/amd_pci_int_defs.h')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 1b5326b88e..448b85e72b 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -63,12 +63,12 @@ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) +#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) #define FCH_INT_TABLE_SIZE 0x63 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ #endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) #define FCH_INT_TABLE_SIZE 0x54 #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ @@ -76,7 +76,7 @@ #define PIRQ_GPP3 0x53 /* GPP INT 3 */ #endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) +#if CONFIG(SOUTHBRIDGE_AMD_PI_KERN) #define FCH_INT_TABLE_SIZE 0x76 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ #define PIRQ_I2C0 0x70 |