diff options
| author | WANG Siyuan <wangsiyuanbuaa@gmail.com> | 2015-08-18 06:22:22 +0800 |
|---|---|---|
| committer | Zheng Bao <zheng.bao@amd.com> | 2015-11-20 05:41:41 +0100 |
| commit | 839d68f1019f9d1a0e57b1429bf1be4685d5e095 (patch) | |
| tree | 3302801f54fec2e14905141ce9b1d0600a378ff7 /src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | |
| parent | 1bb4083859b848b9ffe98ca9fdfbd10adcf482dd (diff) | |
AMD Bettong: refactor PCI interrupt table
1. Use write_pci_int_table to write registers 0xC00/0xC01.
2. Add GPIO, I2C and UART interrupt according
"BKDG for AMD Family 15h Models 60h-6Fh Processors",
50742 Rev 3.01 - July 17, 2015
3. The interrupt valudes are moved from bettong/mptable.c.
All devices work in Windows 10.
Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11746
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/southbridge/amd/pi/hudson/amd_pci_int_defs.h')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 2ace0f037a..679f233f02 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -77,8 +77,14 @@ #endif #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) -#define FCH_INT_TABLE_SIZE 0x75 +#define FCH_INT_TABLE_SIZE 0x76 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +#define PIRQ_I2C0 0x70 +#define PIRQ_I2C1 0x71 +#define PIRQ_I2C2 0x72 +#define PIRQ_I2C3 0x73 +#define PIRQ_UART0 0x74 +#define PIRQ_UART1 0x75 #endif #endif /* AMD_PCI_INT_DEFS_H */ |