diff options
| author | WANG Siyuan <wangsiyuanbuaa@gmail.com> | 2015-05-20 14:41:01 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-06-13 02:22:49 +0200 |
| commit | f2dfef01e1fdf9d8218f0bc6ecfc3f943dc4d2a1 (patch) | |
| tree | 3c0b66ab3395249ddfa4524ebc80bdf3007acc89 /src/southbridge/amd/pi/hudson/acpi/pcie.asl | |
| parent | 597ee56261c75c4e621a83e5999bc84e772ed53f (diff) | |
southbridge/amd/pi: Add support for new AMD southbridge Kern
Kern is the southbridge of AMD Merlin Falcon(Carrizo).
This add support of HD audio, lpc, sata and usb for Kern.
Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10418
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/pi/hudson/acpi/pcie.asl')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/acpi/pcie.asl | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/southbridge/amd/pi/hudson/acpi/pcie.asl b/src/southbridge/amd/pi/hudson/acpi/pcie.asl index dbf4ccbd04..0626cab158 100644 --- a/src/southbridge/amd/pi/hudson/acpi/pcie.asl +++ b/src/southbridge/amd/pi/hudson/acpi/pcie.asl @@ -90,6 +90,14 @@ } IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x60), /* AcpiPm1EvgBlk */ + P1EB, 16, Offset(0xEE), UPWS, 3, } + OperationRegion (P1E0, SystemIO, P1EB, 0x04) + Field (P1E0, ByteAcc, Nolock, Preserve) { + Offset(0x02), + , 14, + PEWD, 1, + } |