diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-01-07 16:55:31 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-19 16:29:00 +0100 |
| commit | ec19fccf7614ae4405829ac0e71460ff18500ee8 (patch) | |
| tree | d5f1ba2e9c337203d5f25b7a6c403f22a7ac8eb3 /src/southbridge/amd/cs5536 | |
| parent | 07651fa3fb8062db4322c64e6faf5643eb96efe7 (diff) | |
google/glados: Set FSP params for min assertion widths and serirq
- Enable serial irq configuration in FSP.
- Set minimum assertion width values for FSP to configure.
- Set I2C4 voltage to 1.8V.
- Enable SaGv feature to dynamically train memory frequency.
- Disable Deep S3 to match chell so DeepSx story is consistent
on skylake-y boards.
BUG=chrome-os-partner:47688
BRANCH=none
TEST=emerge-glados coreboot (tested on chell board)
Change-Id: Ied6bda6a3f2108df7167e0970abe71977d8d2a5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fbf353288edc9629ad03b17d0a582e3042d5a5e1
Original-Change-Id: I1619dd5316060793f38b74f8f0bcaf23d8ab2552
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321211
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13008
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/cs5536')
0 files changed, 0 insertions, 0 deletions